Abstract: A first free port present in a controller or a switch device is physically connected to a second free port present in a switch device (switch device in another storage device unit) other than the controller or switch device comprising the first free port. The possibility of logical connection via a physical path connecting the first free port and second free port is controlled.

Abstract: A system that facilitates maintaining hard disk drive performance comprises a memory component that includes extensions to at least one protocol associated with a hard disk drive, the extensions enable communications to occur in real-time between an operating system and the hard disk drive. An interface component utilizes the extensions to receive a notification from the hard disk drive and relay the notification to the operating system, the notification relates to an operating parameter of the hard disk drive.

Abstract: The present invention provides an interrupt generation circuit that can reduce the time between the moment a monitored object actually enters a desired state and the moment an interrupt is generated. An external event detection unit 101 detects the effective edge of an external event signal. A count period generation circuit 103 generates external event division signals which are counted by the main timer 104 and each of which has a period that is 1/N of the time interval between the effective edges of the immediately preceding external event signal. A compare register 105 stores a value corresponding to the time at which an interrupt is to be generated. When the count value of the main timer 104 becomes equal to or larger than the value stored in the compare register 105, the interrupt determination circuit 106 generated an interrupt.

Abstract: A system and method for optimizing the transmission of signals over a group of wires. In a preferred form of the present invention, a multi-wire bus connects a common card to a plurality of line cards. A framing protocol controls transmissions between the common card and the plurality of line cards. The framing protocol includes a frame having a prefix that identifies in which direction a given transmission will occur. The prefix also identifies over which wire or wires a given line card will receive data. Each of the line cards are configured to interpret the prefix so that at any given time data can be transmitted from the common card to one or more of the line cards by either transmission over a single wire or a plurality of wires.

Abstract: A method, apparatus, and program product access memory resources of a computer using a group of direct access memory (DMA) devices. A first DMA device is designated a primary device after association with an active translation table (ATT), while a second DMA device is designated a backup device after association with an inactive translation table (ITT). A translation is entered into the ATT for the first DMA device to permit it to perform a DMA operation, while a translation is inhibited from being entered into the ITT for a second DMA device to prevent it from performing a DMA operation. Thereafter, the roles of the first and second DMA devices may be swapped by associating the first DMA device with the ITT and associating the second DMA device with the ATT. The computer may be a logically partitioned computer of the type that includes a plurality of logical partitions.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: The present invention relates to a method for disconnecting a transceiver from a bus in multipoint/multidrop architecture. A central processing unit (CPU) and a universal asynchronous receiver transmitter (UART) in a system are connected to a controller used for storing and transmitting data, and the controller is further connected with a bus through a transceiver that monitors/records data and a relay that connects or disconnects the transceiver from the bus. The controller comprises a signal comparator used to compare similarities and differences of data and a failure detection controller used to achieve connection or disconnection of the bus with the transceiver. In case of the transceiver's failure, the controller disconnects the transceiver from the bus to ensure that the bus does not fail to work due to breakdown of the transceiver.

Abstract: Determining an active/standby state for an interface unit includes determining an entity active/standby state for each entity of one or more entities of the interface unit. If each entity active/standby state is standby, then an aggregated active/standby state of the interface unit is established to be standby.

Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.

Abstract: The present invention provides a method for transmitting a non-SCSI command via a SCSI command. A CDB for the SCSI command is provided. The CDB includes bytes byte—0, byte—1, byte—2, . . . , byte_n, in which byte—0 includes an opcode for the SCSI command. An opcode for the non-SCSI command is loaded into byte—1. When the non-SCSI command is not greater than a fixed number of bytes, the non-SCSI command is loaded into at least one byte of the CDB, which includes byte—2. Data associated with the non-SCSI command is transmitted via a data phase associated with the SCSI command.

Abstract: This invention relates to a method of and an apparatus for providing an interface between a client and one or more data storage systems. Existing approaches to the management of multiple, distributed heterogeneous data storage systems are deficient in that they are inflexible to change. To alleviate these deficiencies there is provided a method of providing an interface between a client (307) and one or more data storage systems (309). The method comprises the steps of receiving a request from a client (307), searching, in a rule store populated by modifiable human-readable rules each specifying a handler for use in responding to client requests, for a human readable rule and providing the interface by activating the handler specified in the human readable rule to communicate with the data storage systems.

Abstract: A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

Abstract: An LBA correspondence table creating unit creates an LBA correspondence table to convert address information on a floppy disk which is a copy source into address information on an SD memory card, in relation to an FD image area. If an access to the floppy disk to be emulated is requested, an FD access control unit alternately executes access to the SD memory card on the basis of the LBA correspondence table. An FD exchange emulating unit monitors updating and deletion in an FD image SD area by an HD access control unit. If the access is made, the FD exchange emulating unit executes emulation as if the floppy disk was exchanged.

Abstract: A dual-CPU computer-based multimedia system is provided, including a computer connected to a multimedia playing control module. The multimedia playing control module has a second CPU connected to the computer through a bus, a multimedia activation and playing system memory connected to the second CPU and storing a second operating system and a kernel program, and at least a hotkey, connected to the second CPU through a hotkey interface circuit, with each hotkey corresponding to a multimedia player. When the second PCU detects any hotkey being operated, the second PCU loads the kernel of the second operating system from the multimedia activation and playing system memory and executes the kernel. Then, the second CPU loads and executes the driver and the application program for the multimedia player corresponding to the operated hotkey.

Abstract: A configurable buffer arbiter is provided that combines a time-slot based algorithm, a fairness-based algorithm, and a priority-based algorithm to meet the bandwidth and latency requirements of multiple channels needing access to a buffer memory. The channels have different static and dynamic characteristics. The static channel characteristics include aspects such as a required latency for access to the buffer memory, a required bandwidth to the buffer memory, a preferred latency or bandwidth to the buffer memory, the amount of data the channel can burst in each access to the buffer memory, and the ability for the channel to continuously burst its data to the buffer memory with or without any pauses. The dynamic characteristics include aspects such as whether a channel's FIFO is nearing full or empty, or whether one of the static characteristics has suddenly become more critical. Configuration of the arbiter algorithms exists to optimize the arbiter for both the static and dynamic channel characteristics.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: The present invention provides a method that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from either the local operating system or hypervisor. In one aspect of the present invention, a mechanism is provided for determining whether a user space operation is a resource management operation of a work processing operation. If the user space operation is a resource management operation, appropriate functions are performed to either query, create, modify or destroy resource allocations in the I/O adapter. If the user space operation is a work processing operation, appropriate functions are performed to create work queue entries and inform the I/O adapter of the work queue entries and to retrieve completion queue entries for work queue entries whose processing has been completed by the I/O adapter.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track status for each of the plurality of queues, a status cache to track status for a subset of the plurality of queues that are undergoing processing, and a queuing engine to queue incoming data and de-queue outgoing data. The queuing engine receives and updates the status for the subset of the plurality of queues from the status cache and receives and updates the status for remaining queues from the status storage device.

Abstract: A serial-connection and parallel-communication fast interface for a PLC host and an expansion device includes a PLC host, at least one expansion device and shared bus comprising address lines, data lines, control lines and I/O addressing lines. The PLC host comprises an initial address output circuit and outputting a clamping value to the expander through an output addressing line. The expansion device includes a microprocessor, a memory unit and a clamping and decoding circuit such that the expansion device can automatically allocate the order thereof and output the clamping value through the addressing line. The expansion device can automatically allow or block the data from the PLC host. Therefore, the problem of overlong communication time for data access, the augmentation of expansion device and order limitation can be saved.