Patents Examined by Bryan E. Webster
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Patent number: 5511100Abstract: A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.Type: GrantFiled: December 13, 1993Date of Patent: April 23, 1996Assignee: Motorola, Inc.Inventors: James R. Lundberg, Charles E. Nuckolls
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Patent number: 5509038Abstract: A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and retains the current state of comparison at the start of a transfer of a block or frame of data for determining along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. A phase comparator responds to the phase relationship between clocks attaining a value within one or another range of values at the start of a data frame to determine which one of the multiple data paths transfers the data frame.Type: GrantFiled: April 6, 1994Date of Patent: April 16, 1996Assignee: Hal Computer Systems, Inc.Inventor: Thomas M. Wicki
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Patent number: 5506872Abstract: A signal compression-selection arrangement (19) dynamically trades off signal storage capacity against signal quality, by sacrificing capacity in favor of signal quality whenever capacity is plentiful and sacrificing quality in favor of capacity whenever capacity is scarce. In a messaging system (FIG. 1), the arrangement monitors the amount of storage (14, 15) that is presently free and available for storing new messages, either on a system-wide or per-mailbox basis, and automatically selects a higher compression rate (13) than a presently-applied compression rate (13) to be applied to newly-received messages as the amount of free storage falls below each predetermined threshold. Storage capacity may be freed up by re-compressing (FIG. 3) at the new, higher, compression rate those stored messages that were previously compressed at a lower compression rate.Type: GrantFiled: April 26, 1994Date of Patent: April 9, 1996Assignee: AT&T Corp.Inventor: David S. Mohler
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Patent number: 5497400Abstract: A data communication receiver (10) uses a decision feedback demodulator (32) to remove data from a received signal. Quadrature components of the received signal define a received phase. The received phase is rotated (46) by an amount predicted to compensate for phase and frequency errors. After this rotation, a decision circuit (52) determines the modulation phase for a current symbol. A phase rotator (64) compares the modulation phase with the received phase to generate a measured phase error for the symbol. This measured phase error and measured phase errors from past symbols are averaged in a combination circuit (80) to produce a phase estimate. The past measured phase errors are also processed to determine the amount of change in measured phase error that has occurred over a number of symbols. This processing yields a frequency estimate. A phase rotator (94) merges the frequency and phase estimates for use in compensating a current received phase.Type: GrantFiled: December 6, 1993Date of Patent: March 5, 1996Assignee: Motorola, Inc.Inventors: Lansing M. Carson, Robert J. Burdge
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Patent number: 5495506Abstract: An automatic frequency control apparatus includes a frequency converter, an analog/digital converter, extractor, a storage unit, a controller, and a local oscillator. The storage unit stores unique word frequency modulation models representing time waveforms obtained by modulating, with a unique word, three frequencies which are a frequency equal to that of a desired intermediate-frequency signal, a frequency slightly higher than that of the desired intermediate-frequency signal, and a frequency slightly lower than that of the desired intermediate-frequency signal.Type: GrantFiled: November 22, 1994Date of Patent: February 27, 1996Assignee: NEC CorporationInventor: Takashi Shoji
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Method and circuits for reducing the peak power of the filtered signal transmitted in a digital link
Patent number: 5493587Abstract: The invention relates to a method of reducing the peak power of a signal at the output of the transmit filter of a digital link, e.g. a microwave link. The invention is characterized by the use of a coding in transmission and a decoding in reception, adapted to reduce the peak power of the filtered signal. In the disclosed embodiment, not intended to be limiting, the encoder and the decoder can be realized through simple maps insertable in the baseband part of the system.Type: GrantFiled: July 27, 1993Date of Patent: February 20, 1996Assignee: Alcatel Italia S.p.A.Inventors: Andrea Sandri, Arnaldo Spalvieri -
Patent number: 5488635Abstract: A low complexity adaptive equalizer for use in U.S. digital cellular radios demodulates .pi./4-shifted differentially encoded quadrature phase shift keyed (DQPSK) encoding in the presence of intersymbol interference (ISI) with reduced decoding complexity by employing an estimated received constellation which takes into account channel changes over time and ISI. The complexity is reduced by tracking a reduced number of estimated reference symbol constellation points and taking advantage of the geometry to estimate the remaining symbol constellation points. Branch metrics are also determined with a reduced number of computations.Type: GrantFiled: October 29, 1993Date of Patent: January 30, 1996Assignee: General Electric CompanyInventors: Sandeep Chennakeshu, Ravinder D. Koilpillai, Raymond L. Toy
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Patent number: 5483554Abstract: Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.Type: GrantFiled: November 10, 1992Date of Patent: January 9, 1996Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Gael Clave, Marc Couvrat
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Patent number: 5483556Abstract: A first frame produced by a first terminal is compressed after suppressing certain of the data fields forming it, then transmitted via a safe link through a transmission network into a second frame. This second frame received by a second terminal via the safe link is unpacked-from the fields relating to this safe link, whereupon the remainder of the frame is decompressed. The data fields suppressed for transmission by the first terminal are restored, either by calculation (for example, in the case of a frame checking sequence), or by insertion of a given word (for example, for each flag between frames). This data compressing and decompressing method is carried out in a data circuit-terminating equipment for a synchronous terminal.Type: GrantFiled: August 25, 1993Date of Patent: January 9, 1996Assignee: SAT (Societe Anonyme de Telecommunications)Inventors: Philippe Pillan, Georges Baudoin
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Patent number: 5481567Abstract: The present invention discloses an improvement over existing techniques for transmitting data over voice-band telephone channels by automatically adapting the amount of warping or compression that is applied to a sequence of signal points. A sequence of warped signal points, each of which is related to a respective signal point of a predetermined base constellation according to a warp function, is received in a decoder via a transmission channel having a non-linear component. After each of the received signal points is unwarped using substantially an inverse of the warp function, the average dispersions of the received inner and outer signal points about corresponding sequences of expected signal points are calculated. The difference between the average dispersion of the inner and outer points is then computed and used to update the amount of warping or compression in order to further minimize the effects of the channel non-linearity. The desired amount of warping is communicated to the transmitting encoder.Type: GrantFiled: September 12, 1994Date of Patent: January 2, 1996Assignee: AT&T Corp.Inventors: William L. Betts, Edward S. Zuranski
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Patent number: 5479445Abstract: A transceiver (20) communicates audio and non-audio data between a variety of digital audio sources and sinks. Transceiver (20) has a receiver (34, 38) which communicates data between a modulated digital audio source (12) and an unmodulated digital audio sink (28), and a transmitter (42, 46) which communicates data between an unmodulated digital audio source (22) and a modulated digital audio sink (16). Digital data is transferred from receiver (34, 38) or received in transmitter (42, 46) in one of a plurality of eight formats. Each of the formats is designed to enable transceiver (20) to interface with a variety of digital audio sinks and sources without additional circuitry. A plurality of mode control pins determine the format provided to transceiver (20) when transmitting or receiving digital audio data.Type: GrantFiled: March 24, 1995Date of Patent: December 26, 1995Assignee: Motorola, Inc.Inventors: Kevin L. Kloker, Thomas L. Wernimont
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Patent number: 5473634Abstract: A storage medium (15) has capacity capable of storing data for one frame which is formed by 2.sup.M by 2.sup.N bits. A counter circuit (12) repetitively counts bit numbers of input signals in a range of 1 to 2.sup.M by 2.sup.N, while another counter circuit (13) counts frame numbers. A signal selection circuit (14) specifies addresses the storage medium (15) in an order obtained by successively carrying out N-digit leftward rotation every renewal of the frame number with respect to the count value of the counter circuit (12) expressed in a binary number. A control signal R/W specifies reading and writing in the storage medium (15) every addressing. Thus, data signals DIN belonging to one frame written in the storage medium (15) are read when a next frame is written. The order of the read data signals is leftwardly rotated by N bits with respect to that in writing. Thus, the storage capacity of the storage medium (15) can be halved as compared with the prior art.Type: GrantFiled: May 18, 1994Date of Patent: December 5, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hiroyuki Harada
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Patent number: 5459751Abstract: A demodulation circuit of the communication control system is disclosed, in which the rising edge and the falling edge of a symbol or a one-bit data subjected to pulse width modulation as inputted from a transmission path are detected. The time width of a high-level section or a low-level section of the symbol or the one-bit data is measured on the basis of the result of edge detection. The time width thus measured is compared with a reference time width set in advance. According to the result of comparison, the sampling timing for the high-level section and the low-level section is adjusted respectively. The sampling timing thus adjusted is used to demodulate the data requiring demodulation including the symbol and the one-bit data.Type: GrantFiled: January 6, 1994Date of Patent: October 17, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yasushi Okamoto
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Patent number: 5450448Abstract: Method and apparatus for reducing the contributions of receiver noise signal error and multipath signal error from signals received in a Satellite Positioning System (SATPS) from one or more SATPS satellites by formation and appropriate filtering of differences of signals DD that are differences of SATPS signals received by the SATPS receiver/processor. A difference signal DD of code-phase-derived delta range signals and carder-phase-derived delta range signals is formed, and this difference signal is passed through a first statistical processing filter with an associated time constant .tau.1 in the approximate range 50-500 sec, to produce smoothed or filtered signal with the estimated receiver noise error reduced or removed. The difference signal DD is passed through second and third statistical processing filters having associated time constants .tau.2=5-20 sec and .tau.Type: GrantFiled: April 30, 1993Date of Patent: September 12, 1995Assignee: Trimble Navigation LimitedInventor: Len Sheynblat
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Patent number: 5450452Abstract: A digital loop filter includes a first loop filter for generating first phase control information at variable time intervals on the basis of phase error information indicating a phase difference between a first signal and a second signal. A second loop filter detects a frequency deviation between the first and second signals from the phase error information and generates second phase control information with a period inversely proportional to the frequency deviation. An adder generates finalized phase control information obtained by adding the first phase control information and the second phase control information to each other.Type: GrantFiled: March 3, 1993Date of Patent: September 12, 1995Assignee: Fujitsu LimitedInventors: Mitsuo Kakuishi, Yutaka Awata
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Patent number: 5450440Abstract: In a monitor system in a digital communication apparatus including communication processing blocks on transmission paths of digital data, test data inserting units and data monitor units are arranged such that a monitor interval for the monitor operation in a block overlaps with a monitor period for the monitor operation between adjacent blocks in each processing block. As a result, there is no unmonitored interval in each processing block, thereby achieving a complete monitor operation.Type: GrantFiled: October 22, 1992Date of Patent: September 12, 1995Assignee: NEC CorporationInventors: Motoo Nishihara, Takatoshi Kurano, Kenji Akutsu, Hiromi Ueda
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Patent number: 5450441Abstract: To prevent the occurrence of an anomaly on a single data-sourcing slave channel from causing continuous transmission on that channel and thereby tying up the entirety of a multipoint network, a signal transmission quality monitoring mechanism is incorporated into the office channel unit of each data-sourcing channel. The signal transmission quality monitoring mechanism controls the participation of each monitored digital communications channel on the basis of a measure of the quality of digital signals received from each monitored channel. The control software of each slave channel's office channel unit is configured to include a bipolar violation detector which monitors the channel for the presence of errors exhibited as bipolar violations of alternate mark inversion (AMI)-formatted digital signals. In response to the occurrence of a prescribed number of illegal bipolar violations within a predetermined number of received signals (e.g.Type: GrantFiled: December 14, 1993Date of Patent: September 12, 1995Assignee: AdtranInventors: Norman R. Harris, Don A. Waring, Clint S. Coleman
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Patent number: 5436938Abstract: A phase lock loop (PLL) arrangement includes a voltage controlled ring oscillator (VCRO) including delay elements whose delay is controlled by a control voltage produced by the PLL. A phase error detector is provided which compares pulses of a PLL feedback frequency with pulses of a delayed reference signal, the delay being provided by further delay elements controlled by the same control voltage. The phase error detector produces an output signal which indicates when phase error exceeds a predetermined tolerance, and also indicates an absence of frequency lock.Type: GrantFiled: August 19, 1993Date of Patent: July 25, 1995Assignee: Northern Telecom LimitedInventor: J. P. R. Michel Pigeon
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Patent number: 5430772Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.Type: GrantFiled: March 16, 1993Date of Patent: July 4, 1995Assignees: Electronics and Telecommunications Research Institute, Krea Telecommunication AuthorityInventors: Bhum C. Lee, Kwon C. Park, Hang G. Bahk
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Patent number: RE35137Abstract: A high bit-rate serial communications link encodes data by inserting non-data 0's and 1's. These extra bits are removed by a decoder at the receiving end of the link. Transmission of data can be made along optical fibers.Type: GrantFiled: December 16, 1992Date of Patent: January 2, 1996Assignee: Texas Instruments IncorporatedInventors: Mark A. Bryans, James H. Cline, Francis B. Frazee, Lark E. Lehman