Abstract: Adaptive decision feedback equalizer apparatus for processing information stored on disk or tape media or the like including a data input buffer (34), a gain acquisition circuit (42), a timing acquisition circuit (40) operative to generate timing error signals for controlling the sampling phase of the read signals input to the input buffer, a synchronizing circuit (44) for generating sync detect signals and polarity signals, an FIR filter (36) for generating linear filter output signals, register means (39), feedforward update logic (38) for adjusting the equalizer coefficient signals to develop updated coefficient signals, a dual ported RAM (50) for storing a plurality of the equalizer coefficient signals, feedback logic (48) responsive to the linear filter output signals, equalizer coefficient signals obtained from the RAM, and train data signals, and operative to compute the equalizer error signals and equalizer output signals, feedback update logic (52) for adjusting the values of the coefficient signals

Abstract: Timing jitter in the clock recovery loop of a `blind` signal acquisition receiver employing a square law detector in a phase lock loop signal flow path is substantially reduced by adaptively adjusting the parameters of the loop's pre-filter, so as to compensate for conjugate antisymmetric components in the spectrum of the monitored signal of interest. The signal timing recovery signal processing mechanism includes a filter parameter adjustment operator which controllably sets the weighting parameters of a baseband prefilter, so that the filtered signal does not possess conjugate antisymmetry about the Nyquist frequency and the spectrum of the filtered signal is essentially conjugate symmetric.

Abstract: A phase detecting system is provided for detecting when phase differences which occur between first and second clock pulses from a clock generator exceed acceptable tolerances, regardless of whether the first clock pulse leads the second clock pulse or the second clock pulse leads the first clock pulse. Two identical phase detectors are utilized each of which includes a phase detecting circuit, one group of signal delay elements that allow flip-flops in the phase detecting circuits time to set in order to detect the phase changes, and another group of signal delay elements coupled to the flip-flops which are set so the phase detecting circuit is capable of detecting the nominal phase delay times between the first and second clock pulses.

Abstract: Data communication system between computers; communication paths composed of m transmission lines are formed between two computers, and data to be transferred are coded based on a coding table comprised of encoding codes. When transmitting, state of the m transmission lines 74, 76 and 78 is changed. Therefore, timing signal is not required.

Abstract: A high-throughput bidirectional data communication channel is formed of a pipelined plurality M of stages, connected to the input/output (I/O) port of each of the pair of devices using the channel, and configured to allow interruptibility of data transmission by either device connected to the channel; either device may be sender or receiver and transmission of data may be interrupted by either device for any number of cycles and resumed without loss or duplication of data at the receiver. The channel uses pipelining to achieve longer distance parallel transmission of N plural data bits, while maintaining the maximum high speed throughput. The channel, and its associated data transfer protocol, supports bidirectional transmission of data between the two sourcing/terminating devices with maximum throughput being achieved by transmitting a word of parallel data during every clock cycle.

Abstract: A method of and apparatus for compensating a received signal's phase compensates for the distortion caused by the asymmetrical characteristics of a voltage limiter. This compensation allows the received signal to be sampled at the positive and negative zero-crossings reducing the requirements of a local oscillator in a radiotelephone system. First, the phase of the received signal is sampled at the positive and negative zero-crossings, forming a corresponding positive-crossing and a negative-crossing phase value for the received signal. Second, the negative-crossing and positive-crossing phase values are combined, forming a first difference signal. Third, an estimated error signal is formed using the first difference signal. Fourth, the estimated error signal is combined with the positive or negative zero-crossing phase signals, substantially eliminating the asymmetrical distortion.

Abstract: A method of estimating the carrier frequency of a numeric signal, in which two estimates of the carrier phase are carried out in successive instants of time and the estimated carrier frequency is obtained from the comparison of the above two estimates. The invention also concerns a device for implementing the method, the device including a circuit for estimating the phase of the signal at successive instants in time, a circuit for storing the estimates, and a circuit for comparing the estimates. In a preferred embodiment, both the phase estimator and the comparison circuit are implemented by multipliers and adders.

Abstract: An input signal composed of a predetermined total number of symbols is supplied to a series circuit of delay units. The input signal and delayed output signals from the delay units are multiplied by coefficients, and the products are added into an equalized output signal. The supplied input signal is transmitted, successively in normal, opposite, and normal directions, through a predetermined number of delay units corresponding to a unit number of symbols which is smaller than the predetermined total number of symbols to delay the input signal successively with those delay units. Each time the input signal is transmitted in the series circuit in one of the directions, an amplitude error of the equalized output signal is detected. In order to minimize the amplitude error, coefficients by which to multiply the input signal and the delayed output signals are calculated depending on the detected amplitude error.

Abstract: A data receiving system comprising an I base-band signal and a Q base-band signal which are used in a quadrature demodulation operation. Zero-crossing points of respective base-band signals are detected and a control signal is generated in response to each zero-crossing point. A phase-shift switching circuit alternately selects either the I base-band signal or the Q base-band signal in response to the control signal to generate an I/Q base-band signal. And, a demodulation operation is executed on the basis of the I/Q signal.

Abstract: An adaptive equalization and regeneration system is provided for accurately reconstructing a received data pulse train which has been degraded with respect to amplitude and instantaneous frequency. The system comprises an equalizer which responds to a control signal to provide a variable gain function for the received signal and output an equalized signal, digital phase lock logic for receiving and extracting timing information from the equalized signal, a regenerator for matching the timing information with the equalized signal to reconstruct the received data in its originally transmitted form, and control circuitry for providing the control signal to the equalizer. The control signal adjusts the slope of the equalizer gain function so as to minimize amplitude and instantaneous frequency degradation at the equalizer output. The system includes a mechanism to detect and calculate total signal degradation at the equalizer output.

Abstract: A frequency-offset removal apparatus comprises a receiving section for receiving a signal including a training sequence, a local oscillator for generating an oscillating signal to synchronize with the received signal, a frequency sweeping section for sweeping the frequency of the oscillating signal through a specific frequency which is identical with the carrier frequency of the received signal, a frequency shifting section for shifting the carrier frequency of the received signal by each oscillating signal, a selector for selecting one specific frequency-shifted-signal having the nearest frequency to the specific frequency from the frequency-shifted-signals generated in the frequency shifting section, and a frequency adjusting circuit for adjusting the frequency of the oscillating signal to generate a specific oscillating signal which produces the specific frequency-shifted-signal after shifting by the received signal.

Abstract: Two signals at different frequencies are optionally amplified or attenuated in an automatic gain control amplifier (1) after their reception, then separated from each other by means of band pass filters (2, 5) and amplitude-modulated by means of envelope curve detectors (3, 6), whereupon the envelope curve signals (z.sub.0 [t], z.sub.1 [t]) are sampled by means of sampling switches (4, 7) once per bit to produce sample values (z.sub.0 [kT.sub.b ], z.sub.1 [kT.sub.b ]) which are passed to a calculator unit (8) whose memory stores values of a decision table which are derived from a probability table. Each table area of the latter contains two probability values of which a first is the probability that the sample values (z.sub.0 [kT.sub.b ], z.sub.1 [kT.sub.b ]) lie in the respective table area if the first signal were sent and a second is the probability that the sample values (z.sub.0 [kT.sub.b ], z.sub.1 [kT.sub.b ]) lie in the respective table area if the second signal were sent.

Abstract: A data modem is provided with a boot ROM having a set of instructions for a programmable processor to perform its basic functions within the modem. Enhancements and firmware updates are downloaded over a telephone line through the modem's inherent communications abilities and stored in a battery backed RAM. This permits firmware updates and enhancements to be implemented remotely without need for replacement of ROM or opening of the modem housing.

Abstract: A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval.

Abstract: Receiver having an A/D converter for digitally sampling an analog signal modulated on a carrier frequency at a first sampling frequency, consecutively coupled to a digital quadrature mixer stage for a carrier frequency shift of the digitized modulated signal from the A/D converter, a digital filter device for selecting the phase quadrature signals of the quadrature mixer stage and for decimating the sampling frequency from the first sampling frequency to a second sampling frequency, and a digital demodulation device.

Abstract: A cellular-telephone transmitter (10) employs a vector modulator (14). An integrating circuit (52) generates the integral of the message signal and applies it to circuitry (54, 56) for generating in-phase and quadrature modulation signals representing the cosine and sine, respectively, of the integrating-circuit output. The vector modulator (14) produces the desired FM signal by adding together quadrature and in-phase versions of a carrier in proportion to the values that the quadrature and in-phase modulating signals represent.