Patents Examined by Bryan R Junge
  • Patent number: 10720495
    Abstract: A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Chia-Chun Miao
  • Patent number: 10679916
    Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Sayuri Hada, Kuniaki Sueoka
  • Patent number: 10651230
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a first insulator above the substrate, forming a second insulator on the first insulator, performing a first etching process of etching the second insulator by fluorine and hydrogen contained gas to expose the first insulator while leaving a portion of the second insulator which covers a side face of the gate electrode and performing a second etching process of etching a portion of the first insulator exposed by the first etching process. The first etching process includes a first process and a second process performed after the first process. A reaction product is less deposited in the first process than in the second process and etching selectivity of the second insulator with respect to the first insulator is higher in the second process than in the first process.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 12, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Keita Torii, Takashi Usui, Takuji Mukai
  • Patent number: 10644130
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yuan Yang, Jen-Pan Wang
  • Patent number: 10626495
    Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna
  • Patent number: 10593905
    Abstract: An organic light emitting display device is disclosed, which comprises an anode electrode provided in a light emitting area on a substrate having a plurality of pixels, each pixel including a light emitting area and a transmissive area; an organic light emitting layer on the anode electrode; a cathode electrode on the organic light emitting layer; an auxiliary electrode connected with the cathode electrode; and a connection electrode connected with the anode electrode and provided in the transmissive area of the substrate.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: March 17, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Joonsuk Lee, SeJune Kim, JeongHyeon Choi
  • Patent number: 10553576
    Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 ?m to 5 ?m and a second length along Y-direction between 3 ?m to 5 ?m.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 10522553
    Abstract: A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 10504892
    Abstract: A semiconductor device of a circuit is provided. The circuit is configured to be operated under a power supply. The semiconductor device of the circuit includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region; a first drain region defined by a well and a doped region, wherein the first source region and the doped region are separate by a distance, which is a factor which determines a breakdown voltage of the first transistor, the breakdown voltage being associated with the power supply; and a first gate. The second transistor includes a second source region in a second bulk region, the second source region electrically connected with the first source region and the first gate.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin, Alexander Kalnitsky
  • Patent number: 10494252
    Abstract: The present disclosure provides a CMOS MEMS device. The CMOS MEMS device includes a first substrate, a second substrate, a first polysilicon and a second polysilicon. The second substrate includes a movable part and is located over the first substrate. The first polysilicon penetrates the second substrate and is adjacent to a first side of the movable part of the second substrate. The second polysilicon penetrates the second substrate and is adjacent to a second side of the movable part of the second substrate.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 10497715
    Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Chet E. Carter, Cole Smith, Collin Howder, Richard J. Hill, Jie Li
  • Patent number: 10453687
    Abstract: A method of manufacturing a semiconductor device includes: forming, on a surface of an n-type semiconductor layer, an impurity source film containing both aluminum and beryllium; and forming a p-type impurity-doped layer in the n-type semiconductor layer by irradiating the impurity source film with first laser light to simultaneously introduce the aluminum and the beryllium into the n-type semiconductor layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Patent number: 10453829
    Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Merri Lyn Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, Kevin G. Duesman, James Mathew, Michael P. Violette
  • Patent number: 10446395
    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu, Hui Zang
  • Patent number: 10431604
    Abstract: A display device includes: a substrate including a main display portion, edge portions disposed at edges of the main display portion and including rounded corners, first side portions bent from the edge portions, and second side portions bent from the main display portion; scan lines and data lines that are disposed on the substrate; transistors connected to the scan lines and the data lines; and a data voltage transmission line connected to data lines that are disposed in the first side portions and the edge portions.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Hwan Cho, Jong Hyun Choi, Kyung-Hoon Kim, Dong Hwan Shim, Seon Young Choi
  • Patent number: 10431620
    Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Koichi Baba, Takashi Kubodera, Toshihiko Miyazaki, Hiroaki Ammo
  • Patent number: 10426006
    Abstract: An optoelectronic component includes at least one first carrier with at least two light emitting diodes, wherein the diodes have electrical connections, the electrical connections are led to contact areas, and the contact areas are arranged on an underside of the first carrier; and a second carrier, wherein further contact areas are arranged on a top side of the second carrier, the first carrier bears by the underside on the top side of the second carrier and fixedly connects to the second carrier, and an electronic circuit for open-loop and/or closed-loop control of the power supply of the diodes is integrated in the second carrier.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 24, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Nagel, Stefan Illek
  • Patent number: 10411097
    Abstract: Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Roland Rupp, Christian Hecht
  • Patent number: 10388682
    Abstract: The image sensor includes: a semiconductor substrate having a first conductivity type and including a first surface, a second surface opposite to the first surface, and a well region adjacent to the first surface. A first vertical transfer gate and a second vertical transfer gate are spaced apart from each other and extend in a thickness direction of the semiconductor substrate from the first surface to pass through at least a part of the well region. A photoelectric conversion region has a second conductivity type, which is different from the first conductivity type, is located in the semiconductor substrate between the well region and the second surface, and overlaps the first vertical transfer gate and the second vertical transfer gate in the thickness direction of the semiconductor substrate. A wiring structure is located on the first surface of the semiconductor substrate.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Gu Jin
  • Patent number: 10388818
    Abstract: There is provided a semiconductor detector. According to an embodiment, the semiconductor detector may include a semiconductor detection material including a first side and a second side opposite to each other. One of the first side and the second side is a ray incident side that receives incident rays. The detector may further include a plurality of pixel cathodes disposed on the first side and a plurality of pixel anodes disposed on the second side. The pixel anodes and the pixel cathodes correspond to each other one by one. The detector may further include a barrier electrode disposed on a periphery of respective one of the pixel cathodes or pixel anodes on the ray incident side. According to the embodiment of the present disclosure, it is possible to effectively suppress charge sharing between the pixels and thus to improve an imaging resolution of the detector.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 20, 2019
    Assignee: NUCTECH COMPANY LIMITED
    Inventors: Lan Zhang, Yingshuai Du, Bo Li, Zonggui Wu, Jun Li, Xuepeng Cao, Haifan Hu, Jianping Gu, Guangming Xu, Bicheng Liu