Abstract: A display panel has an active area, and the active area has a camera region. The display panel includes a base, an insulating layer, and a plurality of transparent wirings. The insulating layer is disposed on the base. The insulating layer is provided with a plurality of first grooves located in the camera region. An included angle between a groove wall of a first groove and a surface on which an opening of the first groove is located is less than 90 degrees. The plurality of transparent wirings are disposed on groove walls of the plurality of first grooves.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, an NMOS transistor, and a PMOS transistor. The NMOS transistor includes a first dielectric layer, a first work function layer, and a first conductive layer that are stacked in sequence. The PMOS transistor includes a second dielectric layer, a second work function layer, and a second conductive layer that are stacked in sequence.

Abstract: A semiconductor structure manufacturing method includes: a substrate is provided, and a trench structure is formed in the substrate; a first dielectric layer is formed in the trench structure, and a top surface of the first dielectric layer is lower than a top surface of the trench structure; and a protective layer is formed in the trench structure, and the protective layers at least covers a surface of the first dielectric layer and part of a side wall of the trench structure.

Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a microcavity structure layer and a light emitting structure layer that are stacked, a reflective electrode being disposed in the microcavity structure layer, a groove being disposed on a surface of the microcavity structure layer, the light emitting structure layer including a first electrode disposed in the groove, and the first electrode being connected to the reflective electrode.

Abstract: A display apparatus includes: a substrate; a first display area at which a plurality of main sub-pixels are on the substrate; and a second display area at which a base unit is on the substrate, the base unit comprising a plurality of pixel groups including auxiliary sub-pixels and transmission portions, wherein the pixel groups and the transmission portions are alternately arranged along a first direction, and auxiliary sub-pixels included in one pixel group among the pixel groups are provided in two rows, and a size of an emission area of a first auxiliary sub-pixel among the auxiliary sub-pixels is greater than a size of an emission area of a first main sub-pixel exhibiting a same color as that of the first auxiliary sub-pixel among the main sub-pixels.

Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: An image sensor includes two or more phase-difference detection pixels disposed adjacent to each other, a plurality of general pixels spaced apart from the phase-difference detection pixels, first and second peripheral pixels, and first to third light shields. The first and second peripheral pixels are adjacent to the phase-difference detection pixels, and between the phase-difference detection pixels and the general pixels. The first light shield is disposed in one of the general pixels and has a first width. The second light shield extends into the first peripheral pixel from a first area between the phase-difference detection pixels and the first peripheral pixel, and has a second width different from the first width. The third light shield extends into the second peripheral pixel from a second area between the phase-difference detection pixels and the second peripheral pixel, and has a third width different from the first width.

Abstract: A semiconductor device and method of manufacture comprise forming a channel-less, porous low K material. The material may be formed using a silicon backbone precursor and a hydrocarbon precursor to form a matrix material. The material may then be cured to remove a porogen and help to collapse channels within the material. As such, the material may be formed with a scaling factor of less than or equal to about 1.8.

Abstract: A display device includes a first voltage line disposed on a substrate, a first power supply voltage being applied to the first voltage line, a buffer layer disposed on the first voltage line, a first transistor including a semiconductor pattern disposed on the buffer layer, a first insulating layer disposed on the semiconductor pattern of the first transistor, a first capacitor electrode disposed on the first insulating layer, a second insulating layer disposed on the first capacitor electrode, and a first electrode and a second electrode disposed on the second insulating layer and spaced apart from each other, wherein the second electrode is electrically connected to the first voltage line, and the first voltage line overlaps the first capacitor electrode in a thickness direction of the substrate.

Abstract: An organic light emitting display device is disclosed, which comprises an anode electrode provided in a light emitting area on a substrate having a plurality of pixels, each pixel including a light emitting area and a transmissive area; an organic light emitting layer on the anode electrode; a cathode electrode on the organic light emitting layer; an auxiliary electrode connected with the cathode electrode; and a connection electrode connected with the anode electrode and provided in the transmissive area of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a display pixel in which a bottom electrode and a reflector are separate and border. A light emission device overlies the reflector, and a top electrode overlies the light emission device. A coupling structure extends from the bottom electrode, alongside the reflector, to an interface between the light emission device and the reflector to electrically couple the bottom electrode to the light emission device.

Abstract: The present invention relates to a display panel. In an aspect, a source drain electrode layer in a bending region is provided with grooves at positions corresponding to metal traces and the grooves are filled with a conductive material. By using the conductive material to connect to the metal traces, it does not have to consider stress equilibrium for the metal traces in the bending region, thereby reducing a radius of curvature of the bending and a bezel width and increasing a screen-to-body ratio. In another aspect, a pad plate is provided and the pad plate is provided with conductive bridges arranged at intervals at positions corresponding to the grooves. It can be better connected to the metal traces by the conductive bridges, preventing the conductive material from unable to connect to the metal traces.

Abstract: Methods for selective silicon film deposition on a substrate comprising a first surface and a second surface are described. More specifically, the process of depositing a film, treating the film to change some film property and selectively etching the film from various surfaces of the substrate are described. The deposition, treatment and etching can be repeated to selectively deposit a film on one of the two substrate surfaces.

Abstract: A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

Abstract: A method for manufacturing a MOS transistor includes following. A gate stack structure and a hardmask layer on the gate stack structure are sequentially formed on a substrate. A first spacer is formed on sidewalls of the gate stack structure and the hardmask layer. A photoresist layer is formed on a sidewall of the first spacer. A top surface of the photoresist layer is higher than a top surface of the gate stack structure. The hardmask layer and a portion of the first spacer are removed to expose the top surface of the gate stack structure. A top surface of a remaining first spacer is higher than the top surface of the gate stack structure. The photoresist layer is removed. A second spacer is formed on a sidewall of the remaining first spacer. A top surface of the second spacer is higher than the top surface of the gate stack.

Abstract: A package which comprises a carrier, electronic components mounted on the carrier, an encapsulant at least partially encapsulating the carrier and the electronic components, a clip connected to upper main surfaces of the electronic components, and an electrically conductive bulk connector which is electrically connected with and mounted above the electronic components.

Abstract: An arrangement which has at least one semiconductor module made of silicon carbide, a driver circuit for the at least one semiconductor module, and a cooling system, wherein the at least one semiconductor module and the driver circuit are arranged adjacent to one another, wherein the driver circuit is connected to the cooling system.

Abstract: An organic light emitting display apparatus can include an insulating film disposed on a substrate, a first electrode disposed on the insulating film, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer, wherein the first electrode can be provided with a contact area that covers a contact hole passing through the insulating film, and a protrusion vertically protruded from an upper surface of the first electrode on a boundary surface of the contact hole.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.