Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Abstract: A display device includes a first active pattern disposed on a substrate and including a first material, a second active pattern including a second material that is different from the first material of the first active pattern, a voltage line disposed under the second active pattern, a horizontal transmission line disposed on the second active pattern, and extending in a first direction and a connection pattern spaced apart from the horizontal transmission line, disposed on a same layer as the horizontal transmission line, and making electrical contact with the second active pattern and the voltage line. The horizontal transmission line and the voltage line may be spaced apart from each other and the second active pattern and the voltage line may make contact with each other through the connection pattern. Accordingly, a contact resistance value may be reduced, and a distribution of contact resistance values may resultantly be reduced.

Abstract: A light-emitting device and an electronic apparatus including the same are provided. The light-emitting device includes: a first electrode; a second electrode facing the first electrode; m emission units stacked between the first electrode and the second electrode and including an emission layer; and m?1 charge generation layers each between two neighboring emission units from among the m emission units, wherein m is an integer of 2 or more, at least one of the m emission units includes an inorganic mixed layer between the first electrode and the emission layer, and the inorganic mixed layer includes an inorganic insulating material and an inorganic semiconductor material.

Abstract: A pixel may include a light emitting element; a first transistor electrically connected between a first node and a second node, the first transistor controlling a driving current provided to the light emitting element based on a voltage of a third node; a second transistor electrically connected between a data line providing a data signal and the first node, the second transistor being turned-on in response to a write gate signal; a third transistor electrically connected between the second node and the third node, the third transistor being turned-on in response to a compensation gate signal; and a bias transistor electrically connected between an emission control line providing an emission control signal and the first node, the bias transistor including a gate electrode electrically connected to the first node.

Abstract: After trench etching but before formation of a gate insulating film, a 15-minute to 60-minute heat treatment under a mixed gas atmosphere containing nitric oxide gas and nitrogen gas at a temperature from 1200 degrees C. to 1350 degrees C. and a 30-minute to 75-minute heat treatment under a nitrogen gas atmosphere held at the temperature of the 15-minute to 60-minute heat treatment are successively performed, oxidizing etching damage of inner walls of trenches. The total treatment time of the heat treatments includes a total time of at least 90 minutes when the temperature is a predetermined maximum temperature. The oxide layer of the trench inner walls is removed, exposing a clean face. Emission intensity of band edge emission for SiC obtained by CL analysis of surface areas of the inner walls of the trenches is at least equal to the emission intensity of the band edge emission for SiC obtained by the CL analysis of a surface free of dry etching.

Abstract: A semiconductor device includes first and second active patterns disposed on a substrate, a field insulating film disposed between the first and second active patterns, a first gate structure intersecting the first active pattern, and a second gate structure intersecting the second active pattern, in which the first gate structure includes a first gate insulating film on the first active pattern, a first upper insertion film on the first gate insulating film, and a first upper conductive film on the first upper insertion film, and the second gate structure includes a second gate insulating film on the second active pattern, a second upper insertion film on the second gate insulating film, and a second upper conductive film on the second upper insertion film. Each of the first and second upper insertion films may include an aluminum nitride film. Each of the first and second upper conductive films may include aluminum.

Abstract: A display substrate and a test method thereof are disclosed. The display substrate includes a base substrate, data lines, data leads, a first test circuit and a second test circuit. A display region of the base substrate includes a pixel array, and the pixel array includes a plurality of sub-pixels; the first test circuit is configured to apply a first test signal to the plurality of sub-pixels to perform a first test in a first test stage; the second test circuit is configured to apply a second test signal to the plurality of sub-pixels to perform a second test in a second test stage. The first test circuit includes a first test switch circuit and a first test control signal application circuit, a first test control signal pad and a first test control signal bypass are respectively electrically connected to a control terminal of the first test switch circuit.

Abstract: A miniature light emitting diode chip, a display substrate and a manufacturing method thereof, and a display device are provided. The miniature light emitting diode chip includes: a substrate, including a first side and a second side; a first contact portion and a plurality of contact portions; and a plurality of miniature light emitting diodes. The miniature light emitting diodes each include a first electrode and a second electrode. An orthographic projection of a combination of the plurality of miniature light emitting diodes and a spacing between any two of the plurality of miniature light emitting diodes falls within the substrate. The first electrode of each of the plurality of miniature light emitting diodes is electrically connected to the first contact portion, and the second electrode of each of the plurality of miniature light emitting diodes is electrically connected to the plurality of second contact portions, respectively.

Abstract: A display panel and a display device. The display panel includes: a display area including an optical component area and a regular display area, a first light-emitting device is arranged in the optical component area, a second light-emitting device is arranged in the regular display area, the first light-emitting device is electrically connected with a first pixel circuit, and the second light-emitting device is electrically connected with a second pixel circuit; a transparent conductive layer arranged in the optical component area, the transparent conductive layer includes a connection wire, and the connection wire includes an electrode transition line electrically connected with the first light-emitting device; and a metal external connection line being electrically connected with the electrode transition line and the first pixel circuit respectively outside the optical component area. In the present disclosure, the display effect is ensured while the transparency of the optical component area is ensured.

Abstract: Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.

Abstract: A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.

Abstract: A certain embodiment includes: first wiring layers extended in a first direction arranged in a second direction crossing the first direction; second wiring layers, including two layers having mutually different materials, extended in the second direction arranged in the first direction above the first wiring layers; third wiring layers extended in the first direction arranged in the second direction above the second wiring layers; a first memory cell disposed between one second wiring layer and one first wiring layer between the second and first wiring layers; a second memory cell disposed between one third wiring layer and the one second wiring layer between the third and second wiring layers; a third memory cell disposed between the one second wiring layer and another closest first wiring layer adjacent to the first wiring layer having the first memory cell; and an insulation layer disposed between the first and third memory cells.

Abstract: The present invention provides a display panel, including a substrate (including a flat region and a curved region), a plurality of sub-pixels (including a first sub-pixel, a second sub-pixel, and a third sub-pixel), a packaging layer covering the plurality of sub-pixels, and an optical film layer. The optical film layer includes a plurality of condensation regions and a plurality of transmission regions, the plurality of condensation regions include a first condensation region located on the curved region and disposed corresponding to the first sub-pixel, and the plurality of transmission regions include a first transmission region located on the flat region and disposed corresponding to the first sub-pixel.

Abstract: A display device includes a display element that includes a pixel electrode and a common electrode, a driving thin-film transistor, a first thin-film transistor connected to a gate electrode of the driving thin-film transistor and a first initialization voltage, a second thin-film transistor connected to the pixel electrode of the display element and a second initialization voltage line, and a common voltage line connected to the first initialization voltage line and the second initialization voltage line, wherein a voltage equal to a voltage transmitted to the common electrode is transmitted to the common voltage line.

Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: According to one embodiment, a display device includes a base, a first insulating layer disposed on the base, a first electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and including an opening overlapping the first electrode, a first trench not overlapping the first electrode, and a first surface between the opening and the first trench, an organic layer including a light-emitting layer, and a second electrode covering the organic layer. The organic layer includes a first portion disposed in the opening and covering the first electrode, a second portion disposed on the first surface, and a third portion disposed in the first trench and separated from the second portion.

Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Abstract: A display apparatus includes a display panel including a display element, a first film comprising an elastomeric material and disposed on the display panel, the first film having a first thickness, a first adhesive layer disposed on the first film, the first adhesive layer having a second thickness, and a second adhesive layer disposed between the display panel and the first film and having a third thickness equal to or greater than the second thickness of the first adhesive layer.

Abstract: A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.