Patents Examined by Bryan R Junge
  • Patent number: 12641904
    Abstract: A light receiving element includes a substrate having a first main surface, and includes a light receiving layer provided on the first main surface. The light receiving layer includes a first semiconductor layer and a second semiconductor layer provided on the first semiconductor layer. The light receiving element includes a contact layer provided on the light receiving layer, and includes a groove that separates the contact layer for each pixel. The first semiconductor layer includes a type-II quantum-well layer including an InGaAs layer and a GaAsSb layer. The second semiconductor layer includes a AlxGayIn1-x-yAs layer, where 0?x<1, 0?y<1, and 0<x+y<1. The bottom surface of the groove is situated between a top surface and a bottom surface of the second semiconductor layer, and the light receiving layer includes an n-type region below an exposed portion of a bottom surface of the groove.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: May 26, 2026
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takahiko Kawahara, Kenichi Machinaga
  • Patent number: 12642064
    Abstract: A device includes a die with a protective overcoat and a substrate, the substrate comprising a first region and a second region that are spaced apart. The device also includes an isolation dielectric between the protective overcoat and the die. A pre-metal dielectric (PMD) barrier is between the isolation dielectric and the substrate, the PMD barrier having a first region that contacts the first region of the substrate and a second region that contacts the second region of the substrate, the first region and the second region of the PMD barrier being spaced apart. A through trench filled with a polymer dielectric extends between the first region and the second region of the substrate, and between the first region and the second region of the PMD barrier to contact the isolation dielectric.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 26, 2026
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott Robert Summerfelt, Benjamin Stassen Cook, Sebastian Meier
  • Patent number: 12628514
    Abstract: A display substrate, a manufacturing method therefor, and a display apparatus are disclosed. A display substrate includes a drive circuit layer disposed on a base substrate, the base substrate includes, at least, a first flexible layer, a second flexible layer and a base substrate conductive layer disposed between the first flexible layer and the second flexible layer. The base substrate conductive layer includes, at least, a first connection line, the drive circuit layer includes, at least, a shielding conductive layer and a functional conductive layer, wherein the shielding conductive layer includes, at least, a second connection line, and the functional conductive layer includes, at least, a function signal line. The second connection line is connected with the first connection line through the first lap via, and the function signal line is connected with the second connection line through the second lap via.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: May 12, 2026
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yunpeng Zhang, Yucheng Chan, Chengchung Yang, Yangzhong Jing
  • Patent number: 12563795
    Abstract: A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of ?-Ga2O3 or an ?-Ga2O3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 ?m. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 ?m or greater and 64 ?m or less.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 24, 2026
    Assignee: NGK INSULATORS, LTD.
    Inventors: Hiroshi Fukui, Morimichi Watanabe, Jun Yoshikawa
  • Patent number: 12563821
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 24, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 12557661
    Abstract: A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: February 17, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Yi-Che Chiang, Nien-Fang Wu, Min-Chien Hsiao, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 12550789
    Abstract: A light emitting display apparatus can include a substrate including a display portion; a plurality of pixels disposed in the display portion; a common electrode disposed in the display portion and electrically connected to each of the plurality of pixels; and a pixel common voltage line disposed in the display portion and electrically connected to the common electrode. Also, the light emitting display apparatus can further include at least one closed loop line disposed at an edge portion of the substrate to surround the display portion; at least one cliff pattern portion overlapping with the at least one closed loop line, and a light emitting device layer including a self-light emitting device, disposed on the display portion and the at least one cliff pattern portion, in which the self-light emitting device is isolated by the at least one cliff pattern portion.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: February 10, 2026
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Youngin Jang, KyungMin Kim, HyunDong Kim
  • Patent number: 12543454
    Abstract: The embodiment of the present disclosure provides a display panel and a display apparatus, the display panel includes a base substrate, an electrode layer and a planarization layer. The electrode layer includes a plurality of repeating units, each of which includes at least one electrode set, each of the electrode set includes a plurality of electrode blocks arranged along a first direction, each of the electrode blocks includes a plurality of first electrodes arranged along the first direction and a connection electrode connected between every two adjacent first electrodes. The planarization layer is provided with a plurality of grooves, a corresponding groove of the plurality of grooves is on at least one side of the repeating unit in a second direction. The groove includes a first sidewall extending along the first direction, and at least a portion of the connection electrode is on the first sidewall.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: February 3, 2026
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tongshang Su, Jun Cheng, Yongchao Huang, Jun Liu, Liangchen Yan, Haitao Wang
  • Patent number: 12527168
    Abstract: A transparent display device is provided, which may allow only an area, in which particles occur, to definitely become a dark spot. The transparent display device comprises a plurality of transmissive areas, and a plurality of subpixels disposed between the plurality of transmissive areas. Each of the plurality of subpixels includes a driving transistor including an active layer, a gate electrode, a source electrode and a drain electrode, a light emitting element including a first electrode, a light emitting layer and a second electrode, and a conductive organic layer provided between the driving transistor and the first electrode of the light emitting element to electrically connect the driving transistor with the first electrode.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: January 13, 2026
    Assignee: LG Display Co., Ltd.
    Inventors: MoonSoo Kim, Dohong Kim, Sungbai Lee
  • Patent number: 12506092
    Abstract: A method is provided to form a security barrier of an electronic device under protection. The method includes depositing a transformable dielectric material layer on the electronic device under protection, and converting a target portion of the transformable dielectric material layer into at least one electrical circuit structure having at least one measurable electrical characteristic. The method further includes depositing a thermal stabilizing material layer onto the transformable dielectric material layer.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: December 23, 2025
    Assignee: RAYTHEON COMPANY
    Inventors: Christopher J. Bett, Nathan C. Brown, Craig Alfred Armiento, Peter Alexander Bellus
  • Patent number: 12507467
    Abstract: A method is disclosed for manufacturing a high dielectric constant metal gate of NMOS and PMOS, comprising: step 1, forming an interface layer; step 2, forming a high dielectric constant layer; step 3, performing decoupled plasma nitridation; step 4, performing plasma nitridation annealing with a temperature set below a preset first temperature to reduce the number of oxygen vacancies in the high dielectric constant layer; step 5, forming a P-type work function metal layer; step 6, removing the P-type work function metal layer from the region of the gate structure of the NMOS; step 7, forming an N-type work function metal layer, wherein metal atoms of the N-type work function metal layer of a first NMOS diffuses laterally from an interface to the P-type work function metal layer of adjacent first PMOS and are fixed at the oxygen vacancies by forming a dipole; and step 8, forming the metal gate.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: December 23, 2025
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Weiwei Ma, Ran Huang, Wei Zhou
  • Patent number: 12501694
    Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 16, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shi-You Liu, Ming-Shiou Hsieh, Zih-Hsuan Huang, Tsai-Yu Wen, Yu-Ren Wang
  • Patent number: 12501835
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: December 16, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Jou Lee, Kun-Chen Ho, Hsuan-Hsu Chen, Chun-Lung Chen
  • Patent number: 12490510
    Abstract: A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: December 2, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 12490598
    Abstract: A display device having a bankless structure may comprises: a substrate on which pixels including an emission area and a non-emission area are disposed; a first conductive layer disposed on the substrate, and including a lower electrode of a storage capacitor; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer, and including electrodes of at least one transistor, and an upper electrode of the storage capacitor which is formed in a single pattern with at least one of the electrodes of the at least one transistor; an overcoat layer covering the second conductive layer; and a light-emitting element may be disposed on the overcoat layer, and connected to the upper electrode of the storage capacitor through a via hole, wherein the via hole does not overlap the at least one transistor, when viewed from above.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 2, 2025
    Assignee: LG Display Co., Ltd.
    Inventors: Yongsun Jo, Deuksoo Jung, Woojung Byun, Juhyuk Kim, Youngho Kim, Gunwoo Lee, Hangyu Jung
  • Patent number: 12484387
    Abstract: A method for manufacturing an organic light emitting display apparatus can include forming a transistor on a substrate; forming a planarization film having a lower contact hole on the transistor; forming a connection electrode electrically connected with the transistor through the lower contact hole on the planarization film; and forming an insulating film having a contact hole on the planarization film on which the connection electrode is patterned. Also, the method can further include forming a first electrode having a contact area covering the contact hole on the insulating film and a protrusion vertically protruded on a boundary surface of the contact hole; forming a fence film on the insulating film on which the first electrode is patterned; forming an organic light emitting layer on the first electrode and the fence film; and forming a second electrode on the organic light emitting layer.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: November 25, 2025
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Pureum Kim, Yeonsuk Kang, Hye-Jin Gong
  • Patent number: 12408341
    Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: September 2, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Chet E. Carter, Cole Smith, Collin Howder, Richard J. Hill, Jie Li
  • Patent number: 12388060
    Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: August 12, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Lung Pan, Ting-Hao Kuo, Hao-Yi Tsai, Hsiu-Jen Lin, Hao-Jan Pei, Ching-Hua Hsieh
  • Patent number: 12356812
    Abstract: A display device includes a first active pattern disposed on a substrate and including a first material, a second active pattern including a second material that is different from the first material of the first active pattern, a voltage line disposed under the second active pattern, a horizontal transmission line disposed on the second active pattern, and extending in a first direction and a connection pattern spaced apart from the horizontal transmission line, disposed on a same layer as the horizontal transmission line, and making electrical contact with the second active pattern and the voltage line. The horizontal transmission line and the voltage line may be spaced apart from each other and the second active pattern and the voltage line may make contact with each other through the connection pattern. Accordingly, a contact resistance value may be reduced, and a distribution of contact resistance values may resultantly be reduced.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 8, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Hwan Cho, Wonsuk Choi, Jiryun Park, Seokje Seong, Seungwoo Sung, Hyeonwoo Shin
  • Patent number: 12349533
    Abstract: A light-emitting device and an electronic apparatus including the same are provided. The light-emitting device includes: a first electrode; a second electrode facing the first electrode; m emission units stacked between the first electrode and the second electrode and including an emission layer; and m?1 charge generation layers each between two neighboring emission units from among the m emission units, wherein m is an integer of 2 or more, at least one of the m emission units includes an inorganic mixed layer between the first electrode and the emission layer, and the inorganic mixed layer includes an inorganic insulating material and an inorganic semiconductor material.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: July 1, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongchan Kim, Donghui Lee, Chulsoon Lee, Haemyeong Lee, Wonsuk Han, Yoonseok Ka, Jiyoung Moon, Jihwan Yoon, Heechang Yoon, Jihye Lee, Hakchoong Lee, Yoonhyeung Cho, Myungsuk Han