Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

Abstract: One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the instantiation of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Abstract: In order to detect failure of a charge/discharge current sensor for a battery and estimate and manage the state of charge of the battery when the charge/discharge current sensor has failed, provided are: a state-of-charge estimation unit for estimating the state of charge of the battery; an operation current estimation unit for estimating operation current of an electric load connected to the battery; and a charge/discharge current sensor failure detection unit for determining that failure occurs on the charge/discharge current sensor for detecting charge/discharge current of the battery, when a difference between the charge/discharge current and the operation current estimation value is equal to or greater than a predetermined value, wherein, when failure of the charge/discharge current sensor is detected, the electric load is operated at low output, and the state of charge of the battery is estimated using the operation current estimation value.

Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

Abstract: A communication system comprising: a control line transmitting a control signal for controlling charging of a battery mounted on a vehicle; a reference potential line connected to a reference potential of the vehicle serving as a reference for the control signal; a first PLC communication device connected to the control line and the reference potential line and superposing onto the control signal a differential signal having a higher frequency than the control signal so as to perform communication with an external power supply apparatus; and an inductive element which is provided at a point of connection between the reference potential line 1c and the reference potential or provided in the reference potential line and the inductive element having impedance for a noise having a higher frequency than the control signal is higher than the impedance for the control signal.

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

Abstract: An efficient OPC method of increasing imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and optimizing target gray level for each evaluation point in each OPC iteration based on this function. In one given embodiment, the function is approximated as a polynomial function of focus and exposure, R(?,ƒ)=P0+ƒ2·Pb with a threshold of T+V? for contours, where PO represents image intensity at nominal focus, ƒ represents the defocus value relative to the nominal focus, ? represents the exposure change, V represents the scaling of exposure change, and parameter “Pb” represents second order derivative images. In another given embodiment, the analytical optimal gray level is given for best focus with the assumption that the probability distribution of focus and exposure variation is Gaussian.

Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

Abstract: A roll stabilization system (1) for a motor vehicle which has a DC voltage converter (6) associated with an electric roll stabilizer (2). By way of the DC voltage converter, a feed voltage can be transformed into a supply voltage for the roll stabilizer (2). To produce as compact a structure as possible, the DC voltage converter (6) is integrated in the electric roll stabilizer (2).

Abstract: A wearable device, a charging device for the wearable device and a charging system are disclosed. The wearable device includes a display module and a battery module, and further includes: an optical signal detection module, which is disposed outside the display module and is configured for detecting ambient light; an optical signal demodulation module, which is configured for demodulating modulated light in the ambient light to obtain demodulated light; a photoelectric conversion module, which is configured for converting the demodulated light into an electrical signal. The battery module can receive the electrical signal, so as to be charged by the electrical signal. Without the need to change the existing habits of users, the wearable device can realize charging with the modulated light during a standby state or during being used indoors. Therefore, the charging efficiency of the wearable device is improved.

Abstract: A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: An IC manufacturing model is disclosed, wherein input variables and an output variable are measured using a calibration set of patterns. The model can or cannot include a PSF. The output variable may be a dimensional bias between printed patterns and target patterns or simulated patterns. It can also be a Threshold To Meet Experiments. The input variables may be defined by a metric which uses kernel functions, preferably with a deformation function which includes a shift angle and a convolution procedure. A functional or associative relationship between the input variables and the output variable is defined. Preferably this definition includes normalization steps and interpolation steps. Advantageously, the interpolation step is of the kriging type. The invention achieves a much more accurate modeling of IC manufacturing, simulation or inspection processes.

Abstract: A method for recognizing an over-temperature in a region of a charging socket of a motor vehicle without a temperature sensor. A temperature value is detected by means of a temperature sensor at an installation location of the temperature sensor that is different from the region. At least one configuration value of a current operating configuration in which the charging socket is operated is determined, and then a temperature reading for the region without the temperature sensor is generated by means of a characteristic map, which is designed for the purpose of including the temperature value and the at least one configuration value as input variables and of assigning the temperature reading to these input variables.

Abstract: A non-transitory computer readable storage medium according to an embodiment stores a mask evaluation program evaluating a mask used to manufacture an integrated circuit device. The program causes a computer to realize a convolutional neural network. The convolutional neural network output a calculated value of second data when first data is input. The first data corresponds to a circuit pattern of the mask. The second data corresponds to a pattern formed by the mask. The convolutional neural network has a filter and a weighting coefficient learned to reduce an error of the calculated value and an actual measured value of the second data by using the first data and the actual measured value of the second data.

Abstract: An electronic device includes one or more processors, a display, a primary energy storage device, and an auxiliary energy delivery device. The auxiliary energy delivery device selectively delivers energy to the primary energy storage device. When this occurs, the one or more processors present an icon at least partially superimposed upon a graphical representation of the primary energy storage device on the display.