Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.

Abstract: A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.

Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.