Patents Examined by Bryce P. Bonzo
  • Patent number: 10901879
    Abstract: A computer-implemented method, apparatus and computer program product, the method comprising: obtaining attribute weights associated with element attributes in a web page comprising elements, in regard of a specific element to be operated upon, a first margin, and a second margin; based on the attribute weights, determining a probability for each element in the web page to be the specific element; determining a first threshold indicating a difference between probabilities of two elements having the highest probabilities; determining a second threshold indicating a difference between a probability of an element having the highest probability and one; based on the first threshold, second threshold, first margin and second margin, determining whether the element having the highest probability is the specific element; and subject to the specific element being identified, performing an action upon the specific element.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: January 26, 2021
    Assignee: TESTCRAFT TECHNOLOGIES LTD.
    Inventor: Yarin Podoler
  • Patent number: 10896080
    Abstract: An S.M.A.R.T. threshold optimization method used for disk failure detection includes the steps of: analyzing S.M.A.R.T. attributes based on correlation between S.M.A.R.T. attribute information about plural failed and non-failed disks and failure information and sieving out weakly correlated attributes and/or strongly correlated attributes; and setting threshold intervals, multivariate thresholds and/or native thresholds corresponding to the S.M.A.R.T. attributes based on distribution patterns of the strongly or weakly correlated attributes. As compared to reactive fault tolerance, the disclosed method has no negative effects on reading and writing performance of disks and performance of storage systems as a whole. As compared to the known methods that use native disk S.M.A.R.T. thresholds, the disclosed method significantly improves disk failure detection rate with a low false alarm rate.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 19, 2021
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Song Wu, Zhuang Xiong, Hai Jin
  • Patent number: 10896084
    Abstract: A method, computer program product, and a computer system for mitigating a fault in an information service comprised of multiple microservices includes a processor(s) obtaining a notification of a fault in the information service which includes logs tracking execution of the information service in a shared computing environment. The processor(s) generates a dependency data structure describing interdependencies between individual microservices with respect to each other. The processor(s) mitigates the fault by replacing a faulty microservice in the microservices represented in the dependency data structure; the faulty microservice includes program code with an issue resulting in the fault.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Antonio Bagarolo, Marco Imperia, Paolo Ottaviano, Maximiliano Cammisa, Pasquale Maria Mascolo Montenero
  • Patent number: 10891182
    Abstract: Embodiments are directed to predicting the health of a computer node using health report data and to proactively handling failures in computer network nodes. In an embodiment, a computer system monitors various health indicators for multiple nodes in a computer network. The computer system accesses stored health indicators that provide a health history for the computer network nodes. The computer system then generates a health status based on the monitored health indicators and the health history. The generated health status indicates the likelihood that the node will be healthy within a specified future time period. The computer system then leverages the generated health status to handle current or predicted failures. The computer system also presents the generated health status to a user or other entity.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: January 12, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Hao Xia, Todd F. Pfleiger, Mark C. Benvenuto, Ajay Kalhan
  • Patent number: 10884910
    Abstract: The technology disclosed enables the automatic definition of monitoring alerts for a web page across a plurality of variables such as server response time, server CPU load, network bandwidth utilization, response time from a measured client, network latency, server memory utilization, and the number of simultaneous sessions, amongst others. This is accomplished through the combination of load or resource loading and performance snapshots, where performance correlations allow for the alignment of operating variables. Performance data such as response time for the objects retrieved, number of hits per second, number of timeouts per sec, and errors per second can be recorded and reported. This allows for the automated ranking of tens of thousands of web pages, with an analysis of the web page assets that affect performance, and the automatic alignment of performance alerts by resource participation.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: January 5, 2021
    Assignee: Spirent Communications, Inc.
    Inventor: Brian Buege
  • Patent number: 10877857
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a memory device comprising a plurality of semiconductor devices each including a plurality of memory blocks; and a controller configured to generate at least one or more descriptors in response to a request from a host, and control internal operations of the plurality of semiconductor devices based on the respective at least one or more descriptors. The controller may generate and manage at least one or more descriptor indexes respectively corresponding to the at least one or more descriptors. When a failure occurs during the internal operations of the plurality of semiconductor devices, at least one descriptor corresponding to a memory block in which the failure has occurred is searched for using the at least one or more descriptor indexes.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10853248
    Abstract: It may be beneficial in the case of an undesired lapse of external power to provide a back-up power supply to protect electronic components in an electronic equipment rack. This can frequently be difficult and/or costly due to the necessary addition of electronic infrastructure, such as cabling and/or logic. One means of overcoming this obstacle is to utilize unused or reserved conductors in an already utilized management cable to convey a loss-of-power signal to the components in tandem with the existing cable signals.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Michael Jon Moen
  • Patent number: 10846211
    Abstract: Described herein are technologies related to testing computer code for bugs, wherein the computer code is to run in kernel mode of an operating system. The computer code is executed in kernel mode of a first operating system, and content of memory that is mapped to kernel mode address space of the first operating system is transferred to user mode memory that is mapped to user mode address space of a second operating system. The computer code is executed in user mode and tested while being executed in user mode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Barry C. Bond, Patrice Godefroid
  • Patent number: 10838831
    Abstract: Techniques for remapping portions of an array of non-volatile memory (NVM) resident on a die, in which the die is one of a plurality of NVM dice forming a memory device. A processing device partitions the NVM into a plurality of subslice elements comprising respective physical portions of non-volatile memory having proximal disturb relationships. The NVM has a first portion of the subslice elements allocated as user subslice elements and a second portion as spare subslice elements and the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for a memory domain on the die. For the identified subslice elements having the highest error rates, the processing device remaps user subslice elements to spare subslice elements that were not identified as having the highest error rates to remove subslice element or elements having highest error rates from a user space of the NVM.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 17, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Patent number: 10817396
    Abstract: An application performance management system is disclosed. Operational elements are dynamically discovered and extended when changes occur. Programmatic knowledge is captured. Particular instances of operational elements are recognized after changes have been made using a fingerprint/signature process. Metrics and metadata associated with a monitored operational element are sent in a compressed form to a backend for analysis. Metrics and metadata from multiple similar systems may be used to adjust/create expert rules to be used in the analysis of the state of an operational element. A 3-D user interface with both physical and logical representations may be used to display the results of the performance management system.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 27, 2020
    Assignee: Instana, Inc.
    Inventors: Pavlo Baron, Fabian Lange, Mirko Novakovic, Peter Abrams
  • Patent number: 10802911
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period. The probability of occurrence of the target FBC during the second time period is calculated from a model of FBC distribution change of the set of non-volatile memory cells.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: October 13, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Arthur Shulkin, David Rozman, Tomer Eliash
  • Patent number: 10795784
    Abstract: Faults are managed in a virtual machine network. Failure of operation of a virtual machine among a plurality of different types of virtual machines operating in the virtual machine network is detected. The virtual machine network operates on network elements connected by transport mechanisms. A cause of the failure of the operation of the virtual machine is determined, and recovery of the virtual machine is initiated based on the determined cause of the failure.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 6, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Chen-Yui Yang, Paritosh Bajpay, Chang-Han Jong, Chaoxin Charles Qiu
  • Patent number: 10795756
    Abstract: A system state monitor for managing a distributed system includes a persistent storage and a processor. The persistent storage includes a heuristically derived knowledge base. The processor performs deployment-level monitoring of deployments of the distributed system and identifies a common component failure of components of the deployments based on the deployment-level monitoring. In response to identifying the common component failure, the processor identifies impacted computing devices each hosting a respective component of the components; obtains deployment level state information from each of the impacted computing devices; identifies an iterative set of outcome driven corrective actions based on the obtained deployment level state information and the heuristically derived knowledge base; and initiates a computing device correction on an impacted computing device of the impacted computing devices using the iterative set of outcome driven corrective actions to obtain a corrected computing device.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 6, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Dharmesh M. Patel, Rizwan Ali, Ravikanth Chaganti
  • Patent number: 10795747
    Abstract: Systems, methods, and apparatuses are disclosed for file synchronizing service status monitoring and error handling. A client device includes a local file system access manager that includes a status interface. The status interface is configured to receive a status message from a client-side sync manager of the client device. The client-side sync manager that communicates with a server-side sync manager at a server to synchronize data objects between file systems of the client device and server. The status message corresponds to a state of the client-side sync manager during a multi-stage start-up process for the client-side sync manager. A status caller in an application of the client device can retrieve the status message from the status interface. The status message can also be provided to a user interface for display to a user of the client device, and/or to a telemetry server for use in improving the file synchronizing service.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael J. Novak, Ping Xie, Jack A. Nichols, Valeh Valiollah Pour Amiri, Ioannis Giannoumis
  • Patent number: 10783060
    Abstract: An example embodiment may involve receiving, from a client device, a request to access a web-based resource of a computational instance. One or more server devices disposed within the instance may be configured to be able to execute a plurality of program code units. A software application may be configured to identify one or more of the program code units that, since a previous software release for the instance or in a subsequent software release for the instance, have been modified or added, and store a corresponding change indication for each identified program code unit. The embodiment may also involve, as part of carrying out the request, executing a subset of the program code units, and may further involve generating and providing for display a representation of the web-based resource including a region specifying each of the subset of program code units for which there is a stored change indication.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 22, 2020
    Assignee: ServiceNow, inc.
    Inventors: Kyle James Barron-Kraus, Broc William Oppler
  • Patent number: 10776190
    Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Stark, Ron Gabor, Joseph Nuzman, Raanan Sade, Bryant E. Bigbee
  • Patent number: 10769009
    Abstract: Embodiments of the invention include methods, systems, and computer program products for root cause analysis. Aspects of the invention include receiving, by a processor, operations data associated with a plurality of applications. A trend analysis is performed on the operations data to determine an operations issue associated with at least one of the plurality of applications. And a root-cause analysis is performed on the operations issue to identify a set of candidate applications from the plurality of applications that may be a cause of the operations issue.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yan Luo, Peter Haumer, Gary Mazo
  • Patent number: 10769008
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alberto Manuel Arias Drake, Andrea Iabrudi Tavares, Artur Melo Mota Costa, Fabiano Cruz Peixoto, Laiz Lipiainen Santos, Lucas Ferreira de Melo Diniz, Nathália Peixoto Reis, Patricia Sette Câmara Haizer, Regina Mara Amaral Fonseca, Tamires Vargas Capanema Franco Santos
  • Patent number: 10754759
    Abstract: An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Amitava Majumdar, Georgios Tzimpragos, Jason Villarreal, Kumar Deepak, Jayashree Rangarajan
  • Patent number: 10747714
    Abstract: Described is a framework that manages a clustered, distributed NoSQL data store across multiple server nodes. The framework may include daemons running on every server node, providing auto-sharding and unified data service such that user data can be stored and retrieved consistently from any node. The framework may further provide capabilities such as automatic fail-over and dynamic capacity scaling.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keyan Kousha, Michelle C. Munson, Serban Simu, Ying Xu