Abstract: Techniques for test orchestration are disclosed. A system executes multiple test execution plans, using instances of a same test container image that encapsulates a test environment and instances of at least two different test support container images that are specified by different user-defined test configurations and each configured to perform, respectively, one or more test support operations. To execute each of the test execution plans, the system generates a respective instance of the test container image and one or more test support containers. A particular test execution plan includes generating a test support container that is specified in a corresponding user-defined test configuration and that is different from any test support container specified in another user-defined test configuration.

Abstract: In an embodiment, a system includes a plurality of memory components and a processing device. The processing device includes a command-lifecycle logger component that is configured to perform command-lifecycle-logging operations, which include detecting a triggering event for logging command-lifecycle debugging data, and responsively logging command-lifecycle debugging data. Logging command-lifecycle debugging data includes generating the command-lifecycle debugging data and storing the generated command-lifecycle debugging data in data storage.

Abstract: Methods, apparatus, systems and articles of manufacture for mitigating a firmware failure are disclosed. An example apparatus includes at least one hardware processor and first memory including instructions to be executed by the at least one hardware processor. The example apparatus further includes mask memory including a feature mask associated with a first firmware version, the feature mask identifying features of the first firmware version to be disabled. A platform firmware controller is to apply the first firmware version to the first memory for execution by the at least one processor, initialize the at least one processor using the feature mask, and in response to a detection of a failure, determine a first de-feature mask based on a second de-feature mask previously used by the at least one processor and the feature update mask; and initialize the processor using the first de-feature mask.

Abstract: Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.

Abstract: Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.

Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.

Abstract: Failover methods and systems for a networked storage environment are provided. A filtering data structure and a metadata data structure are generated before starting a replay of a log stored in a non-volatile memory of a second storage node, during a failover operation initiated in response to a failure at a first storage node. The second storage node operates as a partner node of the first storage node to mirror at the log one or more write requests received by the first storage node prior to the failure, and data associated with the one or more write requests. The filtering data structure identifies each log entry and the metadata structure stores a metadata attribute of each log entry. The filtering data structure and the metadata structure are used for providing access to a logical storage object during the log replay from the second storage node.

Abstract: A lifecycle management method, system, and computer program product include coordinating hardware, platform and application-level health checks for framework-independent and application-specific monitoring, failure detection, and recovery, coordinating the hardware, the platform, and the application-level health check by state-specific aggregation of distributed atomic status events, and creating a recovery policy based on the state-specific aggregation of the distributed atomic status events.

Abstract: A method of failure detection in a storage system is performed by the storage system. The method includes detecting a failure in a nonvolatile random access memory device that is in or coupled to a storage device having storage memory. The storage system has multiple NVRAM devices and multiple storage devices that have storage memory. The method includes taking a portion or all of the NVRAM device offline. Taking a portion or all of the NVRAM device offline is responsive to detecting the failure. Taking a portion or all of the NVRAM device off-line is while keeping online the storage memory of the storage device, sufficient ones of the NVRAM devices, and sufficient ones of the storage devices to provide reliable access to data and metadata in the storage system.

Abstract: A smart exception handler system for safety-critical real-time systems is provided. The system is configured to: receive a plurality of parameters at a plurality of nodal points in a real-time execution path; analyze the received parameters using a trained exception handling model, wherein the trained exception handling model has been trained using machine learning techniques to learn the critical path of execution and/or critical range of parameters at critical nodes, wherein the critical range of parameters comprises a learned threshold at a node; compute, using the trained exception handling model, a probability of fault at the critical nodes; compare the probability of fault at a critical node against a learned threshold at the node; and take proactive action in real-time to avoid the occurrence of a fault when the probability of fault at the node is higher than the learned threshold at the node.

Abstract: A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.

Abstract: Failover methods and systems for a storage environment are provided. During a takeover operation to take over storage of a first storage system node by a second storage system node, the second storage system node copies information from a first storage location to a second storage location. The first storage location points to an active file system of the first storage system node, and the second storage location is assigned to the second storage system node for the takeover operation. The second storage system node quarantines storage space likely to be used by the first storage system node for a write operation, while the second storage system node attempts to take over the storage of the first storage system node. The second storage system node utilizes information stored at the second storage location during the takeover operation to give back control of the storage to the first storage system node.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well.

Abstract: Systems and methods for automatically activating self-test devices of sensors of a security system are provided. Such systems and methods can include a self-test monitoring device that can identify a test triggering event and, responsive thereto, activate the self-test devices of the sensors and determine whether each of the sensors passes or fails a respective self-test associated with its self-test devices. In some embodiments, when any of the sensors fails its respective self-test, the self-test monitoring device can identify one or more notification devices based on a type of the test triggering event and transmit a self-test failure report to the one or more notification devices.

Abstract: A method of collecting error logs according to the disclosure includes generating, during procedure of BIOS of a server, at least one BIOS error log based on detection of an error condition of one or more of hardware devices and a CPU, transmitting the at least one BIOS error log to a BMC, storing the at least one BIOS error log received from the CPU, packaging the at least one BIOS error log and at least one log that is generated by the BMC and that is related to BMC sensors to generate an error log file, and storing the error log file.

Abstract: An information processing system includes a plurality of information processing apparatuses each of which includes hardware, a control processor, and a switch circuit wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected, a first switch circuit in the first information processing apparatus is configured to generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses, a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and the second control processor is configured to acquire information transmitted from the first hardware via the signal line.

Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

Abstract: The present invention proposes an information processing system and a volume allocation method making it feasible to reduce overall system operation cost. A replication group to carry out replication is comprised of one or multiple nodes. A storage node classifies respective storage devices mounted thereon into plural storage hierarchies according to the drive type of each of the storage devices for management of the storage devices. A controller node allocates, to each node of the nodes constituting the replication group, a volume for which a storage device of a storage hierarchy suitable for a type of middleware that the node uses and a node type of the node acting in the replication group provides a storage area.

Abstract: A machine learning module is trained by receiving inputs comprising attributes of a computing environment, where the attributes affect a likelihood of failure in the computing environment. In response to an event occurring in the computing environment, a risk score that indicates a predicted likelihood of failure in the computing environment is generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated risk score to an expected risk score, where the expected risk score indicates an expected likelihood of failure in the computing environment corresponding to the event. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve the predicted likelihood of failure in the computing environment.

Abstract: Input on a plurality of attributes of a computing environment is provided to a machine learning module to produce an output value that comprises a risk score that indicates a likelihood of a potential malfunctioning occurring within the computing environment. A determination is made as to whether the risk score exceeds a predetermined threshold. In response to determining that the risk score exceeds a predetermined threshold, an indication is transmitted to indicate that potential malfunctioning is likely to occur within the computing environment. A modification is made to the computing environment to prevent the potential malfunctioning from occurring.