Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.

Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.

Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.

Abstract: The sulfonium salt has high photosensitivity to i-rays and high compatibility with cationically polymerizable compounds such as epoxy compounds, and is excellent storage stability in formulations containing such compounds. The sulfonium salt is represented by general formula (1). In formula (1), R represents an alkyl group or an aryl group; substituents, R1 to R5, each independently represent an alkyl group, a hydroxy group, an alkoxy group, an aryl group, an aryloxy group, a hydroxy(poly)alkyleneoxy group, or a halogen atom; R6 to R9 each independently represent an alkyl group, an aryl group, or a hydrogen atom; m1 to m5 each represent the number of occurrences of each of R1 to R5, m1 and m4 represent an integer of 0 to 3, m2 and m5 represent an integer of 0 to 4, m3 represents an integer of 0 to 5, and X? represents a monovalent polyatomic anion.

Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.

Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate. The first transistor includes a first gate structure, and the second transistor includes a second gate structure. The first gate structure includes a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially formed on the substrate. The second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate. The first capping layer and the second capping layer comprise materials having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

Abstract: A substrate processing method includes a preprocessing forming step of forming a preprocessing film on a surface of a substrate having the surface on which a first region and a second region in which different substances are exposed are present, a preprocessing film separating step of separating the preprocessing film from the surface of the substrate with a stripping liquid, a processing film forming step of forming a processing film on the surface of the substrate after the preprocessing film separating step, and a processing film separating step of separating the processing film from the surface of the substrate with the stripping liquid.

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

Abstract: Printing process in which a substrate to be printed is disposed opposite an ink carrier having an ink layer, wherein the ink layer is regionally heated in such a way that bulges are formed in the ink layer, wherein the bulges contact the substrate and wherein ink splitting is brought about by relative movement between substrate and ink carrier.

Abstract: Embodiments of the present disclosure generally relate to densified nanoimprint films and processes for making these densified nanoimprint films, as well as optical devices containing the densified nanoimprint films. In one or more embodiments, a densified nanoimprint film contains a base nanoimprint film and a metal oxide disposed on the base nanoimprint film and in between the nanoparticles. The base nanoimprint film contains nanoparticles, where the nanoparticles contain titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, hafnium oxide, chromium oxide, indium tin oxide, silicon nitride, or any combination thereof. The metal oxide contains aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, indium oxide, indium tin oxide, hafnium oxide, chromium oxide, scandium oxide, tin oxide, zinc oxide, yttrium oxide, praseodymium oxide, magnesium oxide, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a portion of the photoresist corresponding to a portion of the first stitching region is unexposed during the first light-exposure. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region and a functional feature in the second stitching region, and the portion of the photoresist is exposed by the functional feature during the second light-exposure.

Abstract: Provided are a method of forming a carbon layer and a method of forming an interconnect structure. The method of forming a carbon layer includes providing a substrate including first and second material layers, forming a surface treatment layer on at least one of the first and second material layers, and selectively forming a carbon layer on one of the first material layer and the second material layer. The carbon layer has an sp2 bonding structure.

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer as a mask.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

Abstract: The invention relates to a crosslinkable prepolymer composition for use as a contrast layer. It also relates to a method for structuring an interface material. This method is characterized in particular by the following steps: depositing, on a block copolymer film, a prepolymer composition layer comprising a plurality of functional monomers and at least one crosslinkable functional group within its polymer chain and, on the other hand, two chemically different crosslinking agents, each agent being capable of initiating the crosslinking of said prepolymer in response to a stimulation specific thereto, subjecting the stack to a first stimulation localized on first areas, so as to cause a crosslinking reaction of the molecular chains of said prepolymer, and subjecting the stack to a second stimulation, so as to cause crosslinking of the molecular chains of said prepolymer by the action of said second crosslinking agent in secondary areas.