Patents Examined by Caleen O. Sullivan
  • Patent number: 11454884
    Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 27, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Roman Gouk, Jean Delmas, Steven Verhaverbeke, Chintan Buch
  • Patent number: 11454890
    Abstract: A composition for resist underlayer film formation, includes a compound represented by formula (1) and a solvent. Ar1 represents an aromatic heterocyclic group having a valency of m and having 5 to 20 ring atoms; m is an integer of 1 to 11; Ar2 is a group bonding to a carbon atom of the aromatic heteroring in Ar1 and represents an aromatic carbocyclic group having 6 to 20 ring atoms and having a valency of (n+1) or an aromatic heterocyclic group having 5 to 20 ring atoms and having a valency of (n+1); n is an integer of 0 to 12; and R1 represents a monovalent organic group having 1 to 20 carbon atoms, a hydroxy group, a halogen atom, or a nitro group.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 27, 2022
    Assignee: JSR CORPORATION
    Inventors: Naoya Nosaka, Yuushi Matsumura, Hiroki Nakatsu, Kazunori Takanashi, Hiroki Nakagawa
  • Patent number: 11454887
    Abstract: Disclosed is a method and associated inspection apparatus for measuring a characteristic of interest relating to a structure on a substrate. The inspection apparatus uses measurement radiation comprising a plurality of wavelengths. The method comprises performing a plurality of measurement acquisitions of said structure, each measurement acquisition being performed using measurement radiation comprising a different subset of the plurality of wavelengths, to obtain a plurality of multiplexed measurement signals. The plurality of multiplexed measurement signals are subsequently de-multiplexed into signal components according to each of said plurality of wavelengths, to obtain a plurality of de-multiplexed measurement signals which are separated according to wavelength.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 27, 2022
    Assignee: ASML Netherlands B.V.
    Inventor: Nitesh Pandey
  • Patent number: 11448956
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
  • Patent number: 11450638
    Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: September 20, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dibyajat Mishra, Ashok Prabhu, Tomoko Noguchi, Luu Thanh Nguyen, Anindya Poddar, Makoto Yoshino, Hau Nguyen
  • Patent number: 11443979
    Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Da-Yuan Lee
  • Patent number: 11444035
    Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 13, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee
  • Patent number: 11433608
    Abstract: An imprint apparatus includes: a substrate stage configured to move a substrate; an ejection unit including a plurality of nozzles and configured to eject an ejection material from the nozzles onto the substrate in synchronization with movement of the substrate stage; and a mold driving mechanism configured to drive a mold on which a pattern is formed to press down the mold onto the substrate. The imprint apparatus determines a relative ejection timing of an abnormal nozzle with respect to a normal nozzle based on ejection properties of the nozzles and a moving direction of the substrate stage, determines an ejection timing of the normal nozzle based on the determined relative ejection timing, and controls a synchronization timing of the substrate stage and the ejection unit based on the determined ejection timing of the normal nozzle.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hisashi Namba, Noriyasu Hasegawa
  • Patent number: 11437433
    Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Patent number: 11429026
    Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 30, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Christopher S. Ngai, Ellie Y. Yieh
  • Patent number: 11427684
    Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 30, 2022
    Assignee: Ares Materials, Inc.
    Inventors: Radu Reit, Adrian Avendano-Bolivar, Apostolos Voutsas, David Arreaga-Salas
  • Patent number: 11427464
    Abstract: Embodiments of a packaged electronic device and method of fabricating such a device are provided, where the packaged electronic device includes: a pressure sensor die having a diaphragm on a front side; an encapsulant material that encapsulates the pressure sensor die, wherein the front side of the pressure sensor die is exposed at a first major surface of the encapsulant material; an interconnect structure formed over the front side of the pressure sensor die and the first major surface of the encapsulant material, wherein an opening through the interconnect structure is generally aligned to the diaphragm; and a cap attached to an outer dielectric layer of the interconnect structure, the cap having a vent hole generally aligned with the opening through the interconnect structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 30, 2022
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang, Sandeep Shantaram
  • Patent number: 11424183
    Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 23, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Qi-Zhong Hong, Honglin Guo, Benjamin James Timmer, Gregory Boyd Shinn
  • Patent number: 11409196
    Abstract: Disclosed is a method for forming patterns that can improve line width roughness (LWR) by forming a first resist material on an etch target layer, forming a second resist material including a light-shielding portion and a light-transmitting portion on the first resist material, exposing the first resist material using the light-shielding portion of the second resist material as an exposure mask, removing the second resist material, forming a first resist pattern by developing the exposed first resist material, and etching the etch target layer using the first resist pattern as an etch barrier.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventor: Keun-Jun Kim
  • Patent number: 11409197
    Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a compound represented by Chemical Formula 1, wherein, in Chemical Formula 1, A is a C6 to C30 aromatic moiety, n is an integer of 2 or more, and each B is independently a group represented by Chemical Formula 2,
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Jaebum Lim, Sunghwan Kim, Seunghyun Kim, Taeho Kim, Yushin Park, Sunyoung Yang
  • Patent number: 11409198
    Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a polymer including a structural unit represented by Chemical Formula 1, wherein, in Chemical Formula 1, A is a substituted or unsubstituted dihydroxypyrene moiety, and E is a substituted or unsubstituted pyrenyl group.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Seunghyun Kim, Yushin Park, Hyungseok Park, Sunghwan Kim, Hyeonil Jung
  • Patent number: 11402757
    Abstract: A composition for resist underlayer film formation, includes a compound represented by formula (1) and a solvent. Ar1 represents an aromatic heterocyclic group having a valency of m and having 5 to 20 ring atoms; m is an integer of 1 to 11; Ar2 is a group bonding to a carbon atom of the aromatic heteroring in Ar1 and represents an aromatic carbocyclic group having 6 to 20 ring atoms and having a valency of (n+1) or an aromatic heterocyclic group having 5 to 20 ring atoms and having a valency of (n+1); n is an integer of 0 to 12; and R1 represents a monovalent organic group having 1 to 20 carbon atoms, a hydroxy group, a halogen atom, or a nitro group.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 2, 2022
    Assignee: JSR CORPORATION
    Inventors: Naoya Nosaka, Yuushi Matsumura, Hiroki Nakatsu, Kazunori Takanashi, Hiroki Nakagawa
  • Patent number: 11393694
    Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 19, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Anton Devilliers, Robert Brandt, Jeffrey Smith, Jodi Grzeskowiak, Daniel Fulford
  • Patent number: 11385546
    Abstract: There are provided a plasma-curable multi-level substrate coating film-forming composition for forming a coating film having planarity on a substrate, wherein the composition can fill a pattern sufficiently.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 12, 2022
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Takafumi Endo, Hikaru Tokunaga, Keisuke Hashimoto, Rikimaru Sakamoto
  • Patent number: 11385544
    Abstract: A composition for forming a silicon-containing resist underlayer film contains at least: one or more compounds shown by the following general formula (P-0); and a thermally crosslinkable polysiloxane (Sx), where R100 represents divalent organic group substituted with one or more fluorine atoms; R101 and R102 each independently represent a linear, branched, or cyclic monovalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R103 represents linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom; R101 and R102, or R101 and R103, are optionally bonded to each other to form a ring with sulfur atom in the formula; and L104 represents a single bond or linear, branched, or cyclic divalent hydrocarbon group having 1 to 20 carbon atoms optionally substituted with a hetero-atom or optionally interposed by hetero-atom.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 12, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Yusuke Biyajima, Masahiro Kanayama, Tsukasa Watanabe, Masaki Ohashi