Abstract: A printing plate includes a defined image area having a microstructure pattern. The microstructure pattern is defined by a plurality of rows each having a plurality of diagonal oriented elevated line segments having orientations alternating between a positive angle in one row and a negative angle in an adjacent row, wherein each line segment has a first end aligned with a middle portion of and spaced apart from a first line of a first adjacent row and a second end aligned with a middle portion of and spaced apart from a second line of a second adjacent row. Processes, computer readable media programmed with instructions for performing the processes, and tools for making the printing plate are also described.

Abstract: Described herein is a technique capable of selectively forming a thin film on a substrate while suppressing damage to other films of the substrate. According to the technique, there is provided a method of manufacturing a semiconductor device, including: (a) removing a natural oxide film from a surface of a substrate by supplying a first inorganic material to the substrate wherein a first film and a second film different from the first film are exposed on the surface of the substrate; (b) forming an oxide film by oxidizing a surface of the first film by supplying an oxidizing agent to the substrate; (c) modifying the surface of the first film by supplying a second inorganic material to the substrate; and (d) selectively growing a thin film on a surface of the second film by supplying a deposition gas to the substrate, wherein (a) through (d) are sequentially performed.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: Provided is a preparation method of a semiconductor device, including the following steps: providing a substrate and forming a mask layer with a plurality of first windows on the substrate; forming a dielectric layer, the dielectric layer at least covering sidewalls of the first windows; forming a first photoresist material layer, the first photoresist material layer covering the dielectric layer and the mask layer and filling the first windows; patterning the first photoresist material layer to form a patterned first photoresist layer which exposes a top surface of the dielectric layer; by using the first photoresist layer and the mask layer as masks, removing the dielectric layer to form second windows; and removing part of the substrate along the second windows to form a patterned substrate.

Abstract: A capacitor includes a first electrode including a first reinforcement material having a perovskite crystal structure; and a first metallic material having a perovskite crystal structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, wherein the first metallic material has greater a greater electronegativity than that of the first reinforcement material.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: Provided is a manufacturing method of a flexographic printing plate, including a development step of subjecting a plate surface of a flexographic printing original plate including at least a support, a photosensitive resin composition layer, and an infrared ablation layer sequentially stacked to brushing with a brush while supplying an organic solvent-based developer to the plate surface, wherein the organic solvent-based developer includes 0.1% by mass or more and 10.0% by mass or less of a polymer gel.

Abstract: The present disclosure discloses an overlay mark, an overlay marking method and an overlay measuring method. The overlay marking method includes at least: preparing a first material layer; preparing a first mark group on the first material layer, and the first mark group is a centrally symmetrical pattern; preparing a second material layer on the first material layer; preparing a second mark group corresponding to the first mark group on the second material layer, and the second mark group is a centrally symmetrical pattern; centers of symmetry of the second mark group and the first mark group are located on the same vertical line; preparing a third material layer on the second material layer; preparing a third mark group corresponding to the first mark group and the second mark group on the third material layer, and the third mark group is a centrally symmetrical pattern.

Abstract: Provided in the present invention is a wafer warpage regulation epoxy functional film. The wafer warpage regulation epoxy functional film includes the raw material components, in percentage by mass, 33% of an epoxy resin, 50%-52% of silica, 12%-14% of a curing agent, 1% of a curing accelerator, and 2% of a coloring agent; and the epoxy resin includes a bisphenol F-type epoxy resin and a phenolic epoxy resin. Besides, the above raw material components are stirred and mixed to obtain a slurry, the slurry is coated to a back of a wafer body, and after curing, the epoxy functional film which is formed by the phenolic epoxy resin has high shrinkage and large warpage, to drive the back of the wafer body to warp so as to drive a front of the wafer body to warp backwards.

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: Embodiments of the present disclosure generally relate to densified nanoimprint films and processes for making these densified nanoimprint films, as well as optical devices containing the densified nanoimprint films. In one or more embodiments, a densified nanoimprint film contains a base nanoimprint film and a metal oxide disposed on the base nanoimprint film and in between the nanoparticles. The base nanoimprint film contains nanoparticles, where the nanoparticles contain titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, hafnium oxide, chromium oxide, indium tin oxide, silicon nitride, or any combination thereof. The metal oxide contains aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, indium oxide, indium tin oxide, hafnium oxide, chromium oxide, scandium oxide, tin oxide, zinc oxide, yttrium oxide, praseodymium oxide, magnesium oxide, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Abstract: The disclosure describes an improved drop-on-demand, controlled volume technique for dispensing resist onto a substrate, which is then imprinted to create a patterned optical device suitable for use in optical applications such as augmented reality and/or mixed reality systems. The technique enables the dispensation of drops of resist at precise locations on the substrate, with precisely controlled drop volume corresponding to an imprint template having different zones associated with different total resist volumes. Controlled drop size and placement also provides for substantially less variation in residual layer thickness across the surface of the substrate after imprinting, compared to previously available techniques. The technique employs resist having a refractive index closer to that of the substrate index, reducing optical artifacts in the device.

Abstract: The invention relates to a method for making an individualization zone of a microchip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a conductor layer (30A) comprising via holes (30), the method comprising the following steps: providing at least one dielectric layer (200, 201, 202) having a thickness hd, forming a metal mask layer (300) having a thickness hm and a residual stress ?r on the at least one dielectric layer (200, 201, 202), etching the layer (300) so as to form line patterns (310) of width l, etching the at least one dielectric layer (200, 201, 202) between the line patterns (310) so as to form trenches (210) separated by walls (211), filling the trenches (210) with an electrically conductive material so as to form the electrical tracks (10, 10KO) of the first level (10A), forming via holes (30, 30OK, 30KO1, 30KO2) of the conductor layer (30A), forming the second level (20A) of electrical tracks (20, 20OK), the method being characterized in that the thickn

Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.

Abstract: An object of the present disclosure is to implement a coloring pattern with a constant illuminance value on an electrode substrate to thereby increase display reliability and lifetime while reducing delamination of the hole transport layer (HTL) in the post-process. That is, when the roughness of the pattern after post-baking treatment is low, it may cause delamination of the hole transport layer (HTL) and a decrease in lifetime due to defective pixels, and thus a certain roughness can be obtained by minimizing the surface flow by leaving the substrate at a high temperature during post-baking treatment according to the present disclosure.

Abstract: An embodiment of the present inventive concept provides a display device including: a mother substrate on which a plurality of display modules are located; and a mother film located on a rear surface of the mother substrate, wherein the mother film may include a first layer, and a second layer disposed between the first layer and the mother substrate, the second layer has a thickness of from about 40 ?m to about 60 ?m, and a thickness of the first layer may be greater than that of the second layer.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.