Patents Examined by Caleen O. Sullivan
  • Patent number: 11073762
    Abstract: Provided are an actinic ray-sensitive or radiation-sensitive resin composition which contains (A) a photoacid generator that generates an acid having a pKa of ?1.40 or more upon irradiation with actinic rays or radiation, and (B) a resin having a repeating unit containing an acid-decomposable group, in which an Eth sensitivity of the repeating unit containing an acid-decomposable group is 5.64 or less, and which can provide very excellent roughness performance, exposure latitude, and depth of focus, particularly, in the formation of an ultrafine pattern; a photoacid generator; and an actinic ray-sensitive or radiation-sensitive film, a pattern forming method, and a method for manufacturing an electronic device, each using the actinic ray-sensitive or radiation-sensitive resin composition.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: July 27, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Daisuke Asakawa, Akiyoshi Goto, Masafumi Kojima, Keita Kato, Keiyu Ou, Kyohei Sakita
  • Patent number: 11075111
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Hoon Kim
  • Patent number: 11069815
    Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Auburn University
    Inventors: Minseo Park, Michael C. Hamilton, Shiqiang Wang, Kosala Yapa Bandara
  • Patent number: 11063078
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. A first side of an optically transmissive lid may be coupled to the second side of the semiconductor die through one or more dams. The packages may also include a light block material around the semiconductor package extending from the first side of the semiconductor die to a second side of the optically transmissive lid. The package may include an opening in the light block material on the second side of the optically transmissive lid that substantially corresponds with an active area of the semiconductor die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 13, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Shou-Chian Hsu
  • Patent number: 11056437
    Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 6, 2021
    Assignee: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD.
    Inventors: Kerui Xi, Feng Qin, Jine Liu, Xiaohe Li, Tingting Cui
  • Patent number: 11056605
    Abstract: A detection panel and a manufacturing method of the same are provided. The detection panel includes: a photosensitive element configured to sense a first light beam incident to the photosensitive element to generate a photosensitive signal; a drive circuit configured to be coupled to the photosensitive element to acquire the photosensitive signal from the photosensitive element, the drive circuit including a switch element; and a reflective grating which is on a side of the drive circuit where the first light beam is incident, and is configured to reflect at least a portion of the first light beam incident toward the switch element.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 6, 2021
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Cheng, Yanfei Chi, Xinmao Qiu, Zihua Zhuang, Jin Wang, Changhong Shi, Min Zhou, Yaochao Lv, Yao Liu, Xi Chen
  • Patent number: 11056386
    Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Veeraraghavan S. Basker, Chun-Chen Yeh, Alexander Reznicek
  • Patent number: 11049666
    Abstract: A fabrication method for a flexible bifacial dye-sensitized solar cell is described. The method involves forming a flexible counter electrode of crystalline Pt nanoparticles on a first conductive layer by irradiating a precursor solution with a UV lamp. A flexible photoanode is formed by applying metal oxide particles to a second conductive layer, and then the solar cell is constructed by sandwiching an electrolyte between the counter electrode and photoanode.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 29, 2021
    Assignees: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS, Abdulrahman Bin Faisal University
    Inventors: Idris Kayode Popoola, Muhammad Ashraf Gondal, Jwaher M. Alghamdi, Talal F. Qahtan
  • Patent number: 11049903
    Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Katherine H. Chiang, Chung-Te Lin, Min Cao, Han-Ting Tsai, Pin-Cheng Hsu, Yen-Chung Ho
  • Patent number: 11042089
    Abstract: The present invention relates to a chemically amplified photoresist composition including an alkali-soluble resin and a polymeric photo-acid generator having a predetermined structure, a photoresist pattern produced from the chemically amplified photoresist composition, and a method for preparing the chemically amplified photoresist pattern.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 22, 2021
    Assignee: LG CHEM, LTD.
    Inventors: Min Young Lim, Ji Hye Kim, Yongmi Kim
  • Patent number: 11036135
    Abstract: Provided are: a curable composition having excellent photolithographic properties and resin elution properties; a cured product of the curable composition; and a curing method of the curable composition. The curable composition is characterized by including: (A) at least one selected from the group consisting of a water-soluble polyfunctional (meth)acrylates and water-soluble polyfunctional (meth)acrylamides; and (B) a photosensitive group-containing water-soluble polymer. The water-soluble polyfunctional (meth)acrylates are preferably compounds represented by Formula (I) below, and the water-soluble polyfunctional (meth)acrylamides are preferably compounds represented by Formula (II) below.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 15, 2021
    Assignee: ADEKA CORPORATION
    Inventors: Kenji Hara, Masatomi Irisawa
  • Patent number: 11037952
    Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Patent number: 11030353
    Abstract: In one embodiment, a guide layout creating apparatus includes a selection module that selects a first point as a point on which a guide to array a plurality of particles in a first array is arranged. The apparatus further includes a calculation module that calculates first free energy when the plurality of particles are arrayed in the first array by the guide arranged on the first point, and second free energy when the plurality of particles are arrayed in a second array by the guide arranged on the first point, a type of the second array being different from a type of the first array. The apparatus further includes a determination module that determines whether the first point is employed as the point on which the guide is arranged on the basis of the first free energy and the second free energy.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Sato
  • Patent number: 11022881
    Abstract: A photoacid generator having formula (1a) is provided. A chemically amplified resist composition comprising the PAG forms a pattern of rectangular profile with a good balance of sensitivity and LWR when processed by photolithography using ArF excimer laser, EB or EUV.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 1, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kazuya Honda, Takayuki Fujiwara, Masaki Ohashi, Kazuhiro Katayama
  • Patent number: 11024607
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 11018142
    Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Yasutoshi Okuno
  • Patent number: 11016387
    Abstract: A chemically amplified positive-type photosensitive resin composition containing a predetermined amount of organic solvent (S1) having a boiling point of 120 to 180° C., and satisfying the following requirements: a solvent residual rate measured by the following steps (1) and (2) is 3.5% by mass or less: (1) forming a coated film of 40 ?m by applying the photosensitive resin composition to a substrate; and (2) baking the coated film at a temperature that is higher by 10° C. than the boiling point of the organic solvent (S1) for 30 seconds, and calculating the rate of the organic solvent (S1) in a total mass of the coated film after baking by gas chromatography.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Shota Katayama, Kazuaki Ebisawa
  • Patent number: 11005064
    Abstract: A transparent display substrate and a driving method thereof, and a transparent display device are provided. The transparent display substrate includes a base substrate and pixel units which are located above the base substrate and arranged in an array, each of the pixel units comprises a display region and a transparent region; a first light emitting layer is provided in the transparent region, and a first electrode is provided at a side of the first light emitting layer proximal to the base substrate and a second electrode is provided at a side of the first light emitting layer distal to the base substrate; a brightness of light emitted by the first light emitting layer is adjusted according to change in a difference between a first voltage and a second voltage loaded on the first electrode and the second electrode, respectively.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Meng Li
  • Patent number: 11004799
    Abstract: A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10985115
    Abstract: A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang