Patents Examined by Caleen O. Sullivan
  • Patent number: 11988965
    Abstract: This disclosure relates generally to a patterning structure including an underlayer and an imaging layer, as well as methods and apparatuses thereof. In particular embodiments, the underlayer provides an increase in radiation absorptivity and/or patterning performance of the imaging layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Lam Research Corporation
    Inventors: Samantha S. H. Tan, Jun Xue, Mary Anne Manumpil, Jengyi Yu, Da Li
  • Patent number: 11984317
    Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Marie Krysak, James Blackwell, Lauren Doyle, Brian Zaccheo, Patrick Theofanis, Michael Robinson, Florian Gstrein
  • Patent number: 11982942
    Abstract: The present invention relates to novel positive tone photoresist formulations comprising using crosslinkable siloxane polymers. The siloxane polymers used in the positive tone photoresist formulations are crosslinkable and comprise a first repeating unit, which contains at least one maleimide group, and a second repeating unit, which does not contain a maleimide group. The present invention further provides a manufacturing method for a microelectronic structure using a positive tone photoresist formulation according to the present invention and to an electronic device comprising a microelectronic structure, which is obtained or obtainable by said manufacturing method.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 14, 2024
    Assignee: MERCK PATENT GMBH
    Inventors: Karsten Koppe, Naofumi Yoshida
  • Patent number: 11978660
    Abstract: According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventor: Hirotaka Tsuda
  • Patent number: 11978670
    Abstract: A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Lien Huang
  • Patent number: 11977331
    Abstract: A resist underlayer film that exhibits removability and preferably solubility only in wet etching reagent solutions, while exhibiting good resistance to resist developers that are resist solvents or aqueous alkali solutions. The composition for forming a resist underlayer film includes a dicyanostyryl group-bearing polymer (P) or dicyanostyryl group-bearing compound (C) and includes solvent, and does not contain a protonic acid curing catalyst and does not contain an alkylated aminoplast crosslinking agent derived from melamine, urea, benzoguanamine, or glycoluril.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 7, 2024
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Takafumi Endo, Yuki Endo
  • Patent number: 11980015
    Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fang Chen, Kuo-Chiang Ting, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 11977337
    Abstract: The present document describes a lithographic patterning method for creating features on a surface of a substrate. The patterning method includes the steps of applying a resist material to the substrate surface for providing a resist material layer, selectively exposing, dependent on a location and based on patterning data, the resist material layer to a surface treatment step for chemically modifying the resist material of the resist material layer, and developing, based on the chemical modification of the resist material, the resist material layer such as to selectively remove the resist material. In particular, prior to the step of developing, the method comprises a step of scanning at least a part of the surface using an acoustic scanning probe microscopy method for determining a local contact stiffness of the substrate surface at a plurality of locations, for measuring one or more critical dimensions of the features to be formed on the surface.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 7, 2024
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Diederik Jan Maas, Hamed Sadeghian Marnani, Emile Van Veldhoven
  • Patent number: 11978630
    Abstract: A heat treatment device includes: a heating plate configured to support and heat a substrate on which a resist film is formed; a chamber configured to cover a processing space above the heating plate; a gas supply configured to supply a gas into the chamber along a gas flow path connected to an inside of the chamber, the gas flow path beginning from an outer periphery of the heating plate and extending along an upper surface of the heating toward an end portion on an outer periphery of the substrate; and an exhaust port configured to evacuate inside of the chamber through exhaust holes that are formed above the processing space and open downwards.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: May 7, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yohei Sano
  • Patent number: 11961738
    Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
  • Patent number: 11955336
    Abstract: Method of manufacturing a semiconductor device, includes forming a protective layer over substrate having a plurality of protrusions and recesses. The protective layer includes polymer composition including polymer having repeating units of one or more of: Wherein a, b, c, d, e, f, g, h, and i are each independently H, —OH, —ROH, —R(OH)2, —NH2, —NHR, —NR2, —SH, —RSH, or —R(SH)2, wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not H. R, R1, and R2 are each independently a C1-C10 alkyl group, a C3-C10 cycloalkyl group, a C1-C10 hydroxyalkyl group, a C2-C10 alkoxy group, a C2-C10 alkoxy alkyl group, a C2-C10 acetyl group, a C3-C10 acetylalkyl group, a C1-C10 carboxyl group, a C2-C10 alkyl carboxyl group, or a C4-C10 cycloalkyl carboxyl group, and n is 2-1000. A resist layer is formed over the protective layer, and the resist layer is patterned.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing Hong Huang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 11942522
    Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A substrate provided with a plurality of active areas arranged at intervals is provided. A first laminated structure and a first photoresist layer are sequentially formed on the substrate. Negative Type Develop (NTD) is performed on the first photoresist layer, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess and form a plurality of protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 26, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yexiao Yu, Zhongming Liu
  • Patent number: 11935840
    Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee
  • Patent number: 11926581
    Abstract: The sulfonium salt has high photosensitivity to i-rays and high compatibility with cationically polymerizable compounds such as epoxy compounds, and is excellent storage stability in formulations containing such compounds. The sulfonium salt is represented by general formula (1). In formula (1), R represents an alkyl group or an aryl group; substituents, R1 to R5, each independently represent an alkyl group, a hydroxy group, an alkoxy group, an aryl group, an aryloxy group, a hydroxy(poly)alkyleneoxy group, or a halogen atom; R6 to R9 each independently represent an alkyl group, an aryl group, or a hydrogen atom; m1 to m5 each represent the number of occurrences of each of R1 to R5, m1 and m4 represent an integer of 0 to 3, m2 and m5 represent an integer of 0 to 4, m3 represents an integer of 0 to 5, and X? represents a monovalent polyatomic anion.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 12, 2024
    Assignee: SAN-APRO LIMITED
    Inventors: Takuto Nakao, Yusaku Takashima
  • Patent number: 11927885
    Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Roman Gouk, Jean Delmas, Steven Verhaverbeke, Chintan Buch
  • Patent number: 11921426
    Abstract: A substrate processing method includes a preprocessing forming step of forming a preprocessing film on a surface of a substrate having the surface on which a first region and a second region in which different substances are exposed are present, a preprocessing film separating step of separating the preprocessing film from the surface of the substrate with a stripping liquid, a processing film forming step of forming a processing film on the surface of the substrate after the preprocessing film separating step, and a processing film separating step of separating the processing film from the surface of the substrate with the stripping liquid.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: March 5, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Katsuya Akiyama, Yukifumi Yoshida, Song Zhang
  • Patent number: 11923240
    Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate. The first transistor includes a first gate structure, and the second transistor includes a second gate structure. The first gate structure includes a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially formed on the substrate. The second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate. The first capping layer and the second capping layer comprise materials having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Da-Yuan Lee
  • Patent number: 11914299
    Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Christopher S. Ngai, Ellie Y. Yieh
  • Patent number: 11908940
    Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Pratik A. Patel
  • Patent number: 11908815
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang