Abstract: An object of the present invention is to provide an actinic ray-sensitive or radiation-sensitive resin composition which is capable of forming a pattern having an excellent pattern line width roughness (LWR). In addition, another object of the present invention is to provide: a resist film, a pattern forming method, and a method for manufacturing an electronic device, each of which uses the actinic ray-sensitive or radiation-sensitive resin composition.

Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

Abstract: Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate. The methods may include transferring the substrate to a printing station. The methods may include applying a second chucking force to the substrate to flatten the substrate against a surface of the printing station. The methods may include adjusting a printing pattern based on the mapping of the die pattern. The methods may include printing the printing pattern on the exposed surface of the substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a mold layer on a semiconductor wafer having a plurality of integrated circuit die at least partially defined therein. An etch stopper film is selectively formed on a second portion of the mold layer extending adjacent a periphery of the semiconductor wafer, but not on a first portion of the mold layer extending opposite at least one of the plurality of integrated circuit die. A preliminary pattern layer is formed on the etch stopper film and on the first portion of the mold layer. A plurality of patterns are formed in the preliminary pattern layer by selectively exposing the preliminary pattern layer to extreme ultraviolet light (EUV). Then, hole patterns are selectively formed in the first portion of the mold layer, using the exposed preliminary pattern layer and the etch stopper film as an etching mask.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

Abstract: A resist underlayer film-forming composition including a novolac resin having a structural group (C) formed by reaction between an aromatic ring of an aromatic compound (A) having at least two amino groups and three C6-40 aromatic rings and a vinyl group of an aromatic vinyl compound (B). The structural group (C) may be a group of the following Formula (1): [wherein R1 is a divalent group containing at least two amino groups and at least three C6-40 aromatic rings]. R1 may be a divalent organic group prepared by removal of two hydrogen atoms from aromatic rings of a compound of the following Formula (2): R1 may be a divalent organic group prepared by removal of two hydrogen atoms from aromatic rings of N,N?-diphenyl-1,4-phenylenediamine.

Abstract: Provided is a system for cooling semiconductor components including: a cover body including at least one upper cover and lower cover, which are separated from each other, face each other, and are combined to form a coolant flow path in an inner space thereof; an inlet combined to one side of the cover body and used for a coolant to flow in; an outlet combined to the other side of the cover body and used for the coolant to be discharged; at least one connecting part pin inserted and arranged toward a flowing direction of the coolant in the inner space of the cover body; and insertion grooves formed for the connecting part pins to be inserted in the inner space of the cover body, wherein the upper cover or the lower cover of the cover body is combined to at least one of the upper surfaces or the lower surfaces of semiconductor components by using connecting members so that heat transmitted from the semiconductor components to the connecting part pins is efficiently radiated by enlarging an area contacting the c

Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.

Abstract: An apparatus includes a first processing line including a first cleaving unit adapted for separating a first solar cell into solar cell pieces. The apparatus includes a second processing line including a second cleaving unit adapted for separating a second solar cell into solar cell pieces. The apparatus includes a storing unit adapted for storing a plurality of solar cell pieces. The apparatus is adapted for transferring a solar cell piece from a first position on the first processing line to the storing unit. The apparatus is adapted for transferring the solar cell piece from the storing unit to a second position on the second processing line.

Abstract: A light shielding film made up of a material containing one or more elements selected from silicon and tantalum and a hard mask film made up of a material containing chromium, oxygen, and carbon are laminated on a transparent substrate. The hard mask film is a single layer film having a composition gradient portion with increased oxygen content on the surface and on the neighboring region. The maximum peak for N1s in a narrow spectrum obtained via X-ray photoelectron spectroscopy analysis is the lower limit of detection or less. The portions excluding the composition gradient portion of the hard mask film have a 50 atom % or more chromium content, and the maximum peak for Cr2p in a narrow spectrum obtained via X-ray photoelectron spectroscopy analysis has a binding energy of 574 eV or less.

Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Abstract: A technique for suppressing a metal component from remaining at a bottom of a mask pattern when the mask pattern is formed using a metal-containing resist film. A developable anti reflection film 103 is previously formed below a resist film 104. Further, after exposing and developing the wafer W, TMAH is supplied to the wafer W to remove a surface of the anti-reflection film 103 facing a bottom of the recess pattern 110 of the resist film 104. Therefore, the metal component 105 can be suppressed from remaining at the bottom of the recess pattern 110. Therefore, when the SiO2 film 102 is subsequently etched using the pattern of the resist film 104, the etching is not hindered, so that defects such as bridges can be suppressed.

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

Abstract: A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Abstract: According to one embodiment, a pattern forming method includes: forming a first mask layer on a sample; forming a second mask layer on the first mask layer, the second mask layer containing a first inorganic material and a first organic material; forming a pattern in the second mask layer; oxidizing the first inorganic material and removing at least a portion of the first organic material from the second mask layer by exposing the second mask layer to a first oxidizing gas containing ozone; and transferring the pattern to the first mask layer by etching the first mask layer with the second mask layer.