Abstract: A method for exposing a photopolymerization layer comprising photopolymers includes: providing a printed circuit board, with a photopolymerization layer disposed on the top side of the printed circuit board; performing first-instance exposure on the photopolymerization layer, using a UV source and a digital micro-lens device, wherein the UV source is of a power less than 0.2 kW; stopping the first-instance exposure; covering the photopolymerization layer with a mask, with the mask having a bottom side in contact with the photopolymerization layer; and performing second-instance exposure on the photopolymerization layer, using a mercury lamp and the mask, wherein the mercury lamp is of a power greater than 5 kW.

Abstract: A semiconductor structure, and a method of making the same, includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate including n first regions extending perpendicular to the uppermost surface of the semiconductor substrate and n?1 second regions extending between and connecting each of the n first regions and parallel to the uppermost surface of the semiconductor substrate, wherein n?3.

Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.

Abstract: A semiconductor photoresist composition includes an organometallic compound represented by Chemical Formula 1, an organometallic compound represented by Chemical Formula 2, and a solvent, and a method of forming patterns using the same. When the semiconductor photoresist composition is irradiated with e.g., extreme ultraviolet light, radical crosslinking between Sn-containing units may occur via Sn—O—Sn bond formation, and a photoresist polymer providing excellent sensitivity, small or reduced line edge roughness, and/or excellent resolution may be formed.

Abstract: A method for in-situ wave front detection within an inspection system is disclosed. The method includes generating light with a light source and directing the light to a stage-level reflective mask grating structure disposed on a mask stage. The method includes directing light reflected from the stage-level reflective structure to a detector-level mask structure disposed in a plane of a detector and then collecting, with an optical element, light reflected from the detector-level mask structure. The method includes forming a pupil image on the detector and laterally shifting the stage-level reflective mask, with the mask stage, across a grating period of the stage-level reflective mask grating structure to provide phase reconstruction for lateral shearing interferometry. The method includes selectively impinging light reflected from the optical element on the one or more sensors of the detector.

Abstract: Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.

Abstract: A semiconductor solid state battery has an insulating layer provided between an N-type semiconductor and a P-type semiconductor. The first insulating layer preferably has a thickness of 3 nm to 30 ?m and a dielectric constant of 10 or less. The first insulating layer preferably has a density of 60% or more of a bulk body. The semiconductor layer preferably has a capture level introduced. The semiconductor solid state battery can eliminate leakage of an electrolyte solution.

Abstract: Provided is a resin material for forming an underlayer film which is used to form a resist underlayer film used in a multi-layer resist process, the resin material including a cyclic olefin polymer (I), in which a temperature at an intersection between a storage modulus (G?) curve and a loss modulus (G?) curve in a solid viscoelasticity of the resin material for forming an underlayer film which is as measured under conditions of a measurement temperature range of 30° C. to 300° C., a heating rate of 3° C./min, and a frequency of 1 Hz in a nitrogen atmosphere in a shear mode using a rheometer is higher than or equal to 40° C. and lower than or equal to 200°.

Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Abstract: In one embodiment, a guide layout creating apparatus includes a selection module that selects a first point as a point on which a guide to array a plurality of particles in a first array is arranged. The apparatus further includes a calculation module that calculates first free energy when the plurality of particles are arrayed in the first array by the guide arranged on the first point, and second free energy when the plurality of particles are arrayed in a second array by the guide arranged on the first point, a type of the second array being different from a type of the first array. The apparatus further includes a determination module that determines whether the first point is employed as the point on which the guide is arranged on the basis of the first free energy and the second free energy.

Abstract: A photosensitive resin composition is also provided that includes a polymer precursor selected from a polyimide precursor and a polybenzoxazole precursor; a photo-radical polymerization initiator; and a solvent, in which an acid value of an acid group contained in the polymer precursor and having a neutralization point in a pH range of 7.0 to 12.0 is in a range of 2.5 to 34.0 mgKOH/g, and either the polymer precursor contains a radically polymerizable group or the photosensitive resin composition includes a radically polymerizable compound other than the polymer precursor.

Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.

Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.

Abstract: A substrate processing method includes a preprocessing forming step of forming a preprocessing film on a surface of a substrate having the surface on which a first region and a second region in which different substances are exposed are present, a preprocessing film separating step of separating the preprocessing film from the surface of the substrate with a stripping liquid, a processing film forming step of forming a processing film on the surface of the substrate after the preprocessing film separating step, and a processing film separating step of separating the processing film from the surface of the substrate with the stripping liquid.

Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.

Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A technique for suppressing a metal component from remaining at a bottom of a mask pattern when the mask pattern is formed using a metal-containing resist film. A developable anti reflection film 103 is previously formed below a resist film 104. Further, after exposing and developing the wafer W, TMAH is supplied to the wafer W to remove a surface of the anti-reflection film 103 facing a bottom of the recess pattern 110 of the resist film 104. Therefore, the metal component 105 can be suppressed from remaining at the bottom of the recess pattern 110. Therefore, when the SiO2 film 102 is subsequently etched using the pattern of the resist film 104, the etching is not hindered, so that defects such as bridges can be suppressed.

Abstract: The present application discloses a semiconductor device structure. The semiconductor device structure includes a dielectric layer over a substrate, a first ring structure over the dielectric layer, and a second ring structure over the dielectric layer and surrounding the first ring structure, wherein the first and the second ring structures have a first common center.