Patents Examined by Calvin Lee
  • Patent number: 11078071
    Abstract: Described is a micro-haptic actuator device that can be fabricated with roll-to-roll MEMS processing techniques. The device includes a first body having a first surface and a second, opposing surface, the body has a chamber defined by at least one interior wall, a piston member disposed in the chamber, physically spaced from the at least one interior wall of the chamber, the piston member having a first surface and a second opposing surface. A membrane layer is disposed over and attached to the first surface of the body, with a portion of the membrane attached to the first surface of the piston member. The device also includes a first electrode supported on a second surface the membrane, and a second body that supports a second electrode, with the second body attached to the second surface of the first body.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 3, 2021
    Assignee: Encite LLC
    Inventor: Stephen Alan Marsh
  • Patent number: 11075142
    Abstract: A cooling apparatus for a power semiconductor includes a cooler having a cooling path so that a cooling medium flows therein, and an auxiliary cooling plate of a multi-layered structure joined to a surface of the cooler with which the power semiconductor comes into contact. A method of manufacturing the cooling apparatus includes providing an auxiliary cooling plate of a multi-layered structure, providing a cooler having a cooling path so that a cooling medium flows therein, and joining the auxiliary cooling plate to a surface of the cooler with which the power semiconductor comes into contact, wherein the providing a cooler and the joining the auxiliary cooling plate are performed together in the same brazing process, so that a manufacture of the cooler and the joining the auxiliary cooling plate are simultaneously performed.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 27, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Seok-Jun Kim
  • Patent number: 11069751
    Abstract: A display device including a light source including a first electrode having a light reflectance for a first light of greater than or equal to about 60%; an organic light emitting layer disposed on the first electrode and emitting the first light; and a second electrode disposed on the organic light emitting layer and having a light transmittance in a visible wavelength region of greater than or equal to about 70%, wherein the light source has a first absorption peak in a wavelength region of about 650 nanometers (nm) to about 750 nm or a second absorption peak in a wavelength region of about 550 nm to about 600 nm at a viewing angle of about 55 degrees to about 85 degrees, and a color filter layer disposed above the light source and including a quantum dot configured to convert the first light into a second light.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 20, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG DISPLAY CO., LTD., SAMSUNG SDI CO., LTD.
    Inventors: Tae Gon Kim, Sung Hun Lee, Ji Whan Kim, Shin Ae Jun, Deukseok Chung
  • Patent number: 11069822
    Abstract: Provided are van der Waals (VDW) films comprising one or more transition metal chalcogenide (TMD) films. Also provided are methods of making VDW films. The methods are based on transfer of monolayer TMD films under vacuum, for example, using a handle layer. Also provided are apparatuses and devices comprising one or more VDW film.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 20, 2021
    Assignee: CORNELL UNIVERSITY
    Inventors: Jiwoong Park, Kibum Kang, Hui Gao, Saien Xie, Kan-Heng Lee
  • Patent number: 11063131
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 11056521
    Abstract: An imaging device, includes: an imaging unit in which are disposed a plurality of pixels, each including a filter that is capable of changing a wavelength of light passing therethrough to a first wavelength and to a second wavelength and a light reception unit that receives light that has passed through the filter, and that captures an image via an optical system; an analysis unit that analyzes the image captured by the imaging unit; and a control unit that controls the wavelength of the light to be transmitted, by the filter based upon a result of analysis by the analysis unit.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 6, 2021
    Assignee: NIKON CORPORATION
    Inventor: Sota Nakanishi
  • Patent number: 11056468
    Abstract: A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, where the second die is aligned to the first die with less than 800 nm alignment error, where the second die includes at least two second alignment marks positioned close to a second die edge of the second die, and where the third die is bonded to the first d
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: July 6, 2021
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 11050030
    Abstract: An organic light-emitting diode (OLED) display screen and an OLED display device are provided. The OLED display screen has a first display region, a second display region, and a folded display region. A bonding region is disposed on a side edge of the second display region away from the folded display region. Only part of a first backplate disposed on the second display region close to the bonding region is retained and replaced with a buffer layer to ensure stability of a shape of the folded display region and prevent wave warping.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 29, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Zhitao Zhu
  • Patent number: 11043446
    Abstract: A semiconductor package includes a connection structure including a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a first connection via penetrating through the first insulating layer and connected to the first redistribution layer, a semiconductor chip disposed on the connection structure, an encapsulant covering at least a portion of the semiconductor chip, a second insulating layer disposed on the encapsulant, a second redistribution layer including a signal line disposed on the encapsulant, and a heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungsoo Park, Kyoungmoo Harr, Jihyun Lee, Doohwan Lee, Junggon Choi
  • Patent number: 11038011
    Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Lili Cheng, Robert J. Fox, III, Luke England
  • Patent number: 11038001
    Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: June 15, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Teruyuki Ueda, Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Tetsuo Kikuchi, Toshikatsu Itoh, Kengo Hara
  • Patent number: 11031431
    Abstract: A semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 8, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto
  • Patent number: 11018072
    Abstract: A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
  • Patent number: 11011507
    Abstract: A 3D semiconductor device, the device including: a first die comprising first transistors and a first interconnect; and a second die comprising second transistors and a second interconnect, wherein said first die is overlaid by said second die, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is pretested, wherein said second die is bonded to said first die, wherein said bonded comprises metal to metal bonding, wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 18, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 11011473
    Abstract: Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younhee Kang, Byoung-Gug Min, Shi-Kyung Kim, Min-Woo Song, Jae-Seon Hwang
  • Patent number: 11011599
    Abstract: Disclosed herein are a stretchable display panel and a stretchable device. The stretchable display panel comprises: a lower substrate having an active area and a non-active area surrounding the active area; a plurality of individual substrates disposed on the lower substrate, spaced apart from each other and located in the active area; a connection line electrically connecting a pad disposed on the individual substrate; a plurality of pixels disposed on the plurality of individual substrates; and an upper substrate disposed above the plurality of pixels, wherein the modulus of elasticity of the individual substrates is higher than that of at least one part of the lower substrate.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 18, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Eunah Kim, Hyunju Jung
  • Patent number: 11011374
    Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a sapphire substrate preparation step S10 for preparing a sapphire substrate having, as a main surface, a {10-10} plane or a plane obtained by inclining the {10-10} plane at a predetermined angle in a predetermined direction; a heat treatment step S20 for performing a heat treatment over the sapphire substrate while performing a nitriding treatment or without performing the nitriding treatment; a buffer layer forming step S30 for forming a buffer layer over the main surface of the sapphire substrate after the heat treatment; and a growth step S40 for forming a group III nitride semiconductor layer, in which a growth surface has a predetermined plane orientation, over the buffer layer, in which at least one of a plane orientation of the main surface of the sapphire substrate, presence or absence of the nitriding treatment during the heat treatment, and a growth temperature in the buffer layer forming step is adjusted such that the
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: May 18, 2021
    Assignee: FURUKAWA CO., LTD.
    Inventors: Yasunobu Sumida, Yasuharu Fujiyama
  • Patent number: 11004764
    Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Tao Hong, Tino Karczewski, Matthias Lassmann, Christian Schweikert
  • Patent number: 10998292
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Bongsub Lee, Guilian Gao
  • Patent number: 10995552
    Abstract: A downhole closed loop method for controlling a drilling toolface includes measuring first and second attitudes of the subterranean borehole at corresponding first and second upper and lower survey stations. The first and second attitudes are processed downhole while drilling to compute an angle change of the subterranean borehole between the upper and lower survey stations. The computed angle change is compared with a predetermined threshold. This process may be continuously repeated while the angle change is less than the threshold. The first and second attitudes are further processed downhole to compute a toolface angle when the angle change of the subterranean borehole is greater than or equal to the threshold. The toolface angle may then be further processed to control a direction of drilling of the subterranean borehole.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 4, 2021
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Peter Hornblower, Christopher C. Bogath, Adam Bowler, Junichi Sugiura