Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Abstract: A device may include: a highly doped n+ Si region; an intrinsic silicon multiplication region disposed on at least a portion of the n+ Si region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped p? Si charge region disposed on at least part of the intrinsic silicon multiplication region, the p? Si charge region having a thickness of about 40-60 nm; and a p+ Ge absorption region disposed on at least a portion of the p? Si charge region; wherein the p+ Ge absorption region is doped across its entire thickness. The thickness of the n+ Si region may be about 100 nm and the thickness of the p? Si charge region may be about 50 nm. The p+ Ge absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/°C.

Abstract: A display apparatus includes: a substrate including a substantially flat area and a curved area extending from the substantially flat area; a first pixel electrode arranged in the curved area; a first emission layer disposed on the first pixel electrode; a second pixel electrode arranged in the substantially flat area; a second emission layer disposed on the second pixel electrode; a first functional layer having a first thickness disposed between the first pixel electrode and the first emission layer; and a second functional layer having a second thickness disposed between the second pixel electrode and the second emission layer. The first thickness is greater than the second thickness.

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

Abstract: The proposed device comprises a plurality of electroactive material actuator units arranged as a set. Control data for driving individual units is transferred over three shared power lines. The electroactive material actuator of each unit is driven depending on control data received from the power lines via a demodulator, a controller, and a driver.

Abstract: An imaging device, includes: an imaging unit in which are disposed a plurality of pixels, each including a filter that is capable of changing a wavelength of light passing therethrough to a first wavelength and to a second wavelength and a light reception unit that receives light that has passed through the filter, and that captures an image via an optical system; an analysis unit that analyzes the image captured by the imaging unit; and a control unit that controls the wavelength of the light to be transmitted, by the filter based upon a result of analysis by the analysis unit.

Abstract: A light emitting device includes a metal reflective layer including a phase modulation surface on which oblong phase modulation elements are formed; a first electrode provided on the metal reflective layer; an organic emission layer that is provided on the first electrode and that emits light; and a second electrode provided on the organic emission layer, wherein the oblong phase modulation elements are arranged to form a geometric phase lens.

Abstract: Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

Abstract: An organic light-emitting device and an apparatus including the same are disclosed. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode. The organic layer includes an emission layer, the emission layer includes a first compound, a second compound, a third compound, and a fourth compound, the first compound is represented by Formula 1, the second compound is represented by Formula 2, the third compound is represented by Formula 3, the fourth compound is represented by any one of Formulae 4-1 to 4-3, each as respectively described in the detailed description.

Abstract: A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

Abstract: An integrated circuit system, structure and/or component is provided that includes an integrated electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. An energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

Abstract: A display including a bending region is provided. The display includes a pixel layer including a plurality of pixel and a substrate disposed under the pixel layer and including a first area on which the pixel layer is disposed and a second area extending out of the pixel layer from the first area, at least a partial area of the second area being bendable, wherein the substrate includes: a wiring layer including at least one first wiring electrically connected with at least one pixel of the plurality of pixels and connected from the first area to the second area, and at least one second wiring disposed in the at least partial area and electrically connected with the at least one first wiring in the second area. Further, other embodiments may be possible.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric, wherein the field electrode comprises a first layer and a second layer, wherein the first layer has a lower electrical resistance than the second layer, wherein a portion of the second layer is disposed above and directly contacts a portion of the first layer.