Patents Examined by Calvin Lee
  • Patent number: 11404600
    Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Jeb Wu, Daniel Brodoceanu, Zheng Sung Chio, Tennyson Nguty, Oscar Torrents Abad, Ali Sengul
  • Patent number: 11404488
    Abstract: A transparent display panel and a display device are disclosed. The orthographic projection of light-emitting region of electroluminescent structure on a base substrate overlaps with the orthographic projection of the region of the pixel circuit on the base substrate to form an overlap region, so that the area occupied by the electroluminescent structures in the sub-pixels is enlarged, thus increasing the pixel aperture ratio of the transparent display panel at the sides, away from the pixel circuits, of the electroluminescent structures.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 2, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Qinghua Zou, Ruhui Zhu, Tingyuan Duan, Fengli Wang
  • Patent number: 11404478
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes row lines, insulating lines extending parallel to the row lines, column lines intersecting with the row lines and the insulating lines and disposed over the row lines and the insulating lines, memory cells respectively disposed at intersections between the row lines and the column lines, and dummy memory cells respectively disposed at intersections between the insulating lines and the column lines.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventor: Young Sam Lee
  • Patent number: 11398545
    Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Han Wui Then
  • Patent number: 11393896
    Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface that face each other in a thickness direction, the first main surface containing a trench; an insulation layer on a surface of the trench; a first electrode layer on the insulation layer; a first dielectric layer on the first electrode layer; and a second electrode layer on the first dielectric layer, in which a thickness (L1) of the insulation layer, a thickness (L2) of the first electrode layer, and a thickness (L4) of the second electrode layer satisfy L1>L2>L4.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: July 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koichi Nishita, Masaki Takeuchi, Yutaka Takeshima, Kazuhiro Inoue
  • Patent number: 11393967
    Abstract: A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer arranged on at least part of the first semiconductor layer, a second semiconductor layer arranged on the light emitting layer; a first metal layer arranged on at least part of the first semiconductor layer and in contact with the first semiconductor layer; an insulating layer covered a surface of the light emitting structure; and an electrode layer arranged on the insulating layer and having at least one region that is not overlapped with the first metal layer or the second metal layer in a vertical direction.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 19, 2022
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Anhe He, Suhui Lin, Jiansen Zheng, Kangwei Peng, Xiaoxiong Lin, Chenke Hsu
  • Patent number: 11393947
    Abstract: The present application provides a method of fabricating a light-emitting diode (LED) display panel, including the following steps: forming an LED substrate including a first substrate, an LED chip disposed on the first substrate, and a first electrode disposed on the LED chip; forming a driving substrate including a second substrate and a second electrode disposed on the second substrate; activating surfaces of the first electrode and the second electrode; aligning and pre-bonding the first electrode with the second electrode; and bonding the first electrode and the second electrode.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: July 19, 2022
    Inventor: Yang Sun
  • Patent number: 11387383
    Abstract: A method of transferring a light emitting device including the steps of preparing a wafer including a substrate, semiconductor layers disposed on the substrate, and bump pads disposed on the semiconductor layers and arranged in a plurality of light emitting device regions, dividing the wafer into a plurality of light emitting devices, attaching the light emitting devices to a transfer tape disposed on a supporting substrate, such that the substrate contacts the transfer tape, preparing a circuit board including pads arranged thereon, adjoining the supporting substrate with the circuit board, so that the bump pads of at least one light emitting device contact the pads of the circuit board, bonding the at least one light emitting device to the pads by applying heat to the bump pads and the pads, and separating the at least one light emitting device bonded to the pads from the transfer tape.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 12, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 11387206
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11387157
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11387170
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11380740
    Abstract: The present application discloses a display panel and a display device. The display panel includes a substrate; an active switch, which is arrange on the substrate and includes a first active switch and a second active switch; a pixel, which is arrange on the substrate and coupled to the first active switch and includes a quantum dot light-emitting diode; and a light sensor, which is arrange on the substrate and coupled to the second active switch and includes a quantum dot light sensing layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 5, 2022
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: En-Tsung Cho
  • Patent number: 11380599
    Abstract: There is provided a semiconductor module including: a base for semiconductor cooling; a stacked substrate provided above the base; a semiconductor chip provided above the stacked substrate; a coating layer provided on an upper surface of the semiconductor chip; and a sealing resin for sealing the semiconductor chip, in which the base is in contact with the sealing resin.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kohei Yamauchi, Tatsuhiko Asai
  • Patent number: 11373856
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 28, 2022
    Assignee: Soitec
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Patent number: 11374181
    Abstract: Provided are a compound of Formula I Ir(LA)x(LB)y(LC)z, where x is 1 or 2; y is 1 or 2; z is 0, or 1, with x+y+z=3; LA is a ligand of Formula II
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: June 28, 2022
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Morgan C. MacInnis, Zhiqiang Ji, Jui-Yi Tsai, Alexey Borisovich Dyatkin, Pierre-Luc T. Boudreault
  • Patent number: 11373898
    Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 28, 2022
    Assignee: Soitec
    Inventors: Daniel Delprat, Damien Parissi, Marcel Broekaart
  • Patent number: 11374204
    Abstract: An organic light emitting diode display panel and an electronic device is provided. Light being incident with a specific angle to an interface between a filling portion and at least one film layer causes total reflection to reduce light being incident into the film layer surrounding the inner wall of the through hole, such that an amount of light after the total reflection reached the substrate and passed through the substrate and received by the optical sensor is increased.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 28, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Simin Peng
  • Patent number: 11367494
    Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Shih-Hao Lin, Jui-Lin Chen, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11362138
    Abstract: An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: June 14, 2022
    Assignee: FACE INTERNATIONAL CORPORATION
    Inventors: Clark D. Boyd, Bradbury R Face, Jeffrey D Shepard
  • Patent number: 11355422
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: June 7, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll