Abstract: A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connec

Abstract: A piezoelectric component that has a piezoelectric element including a piezoelectric ceramic layer and a sintered metal layer on at least a first main surface of the piezoelectric ceramic layer and containing a non-precious metal, and a protective layer containing an elastic body covering first and second opposed main surfaces of the piezoelectric element. The piezoelectric ceramic layer contains 90 mol % or more of a perovskite compound that contains niobium, an alkali metal, and oxygen. A thickness of the piezoelectric element is 100 ?m or less.

Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: An apparatus incorporating a multi-surface heat sink may comprise an integrated circuit die, a heat spreader, a plate element, and a heat sink. The heat spreader may be positioned above the IC die. The plate element may be positioned above the heat spreader. A bottom surface of the heat sink may have a first region positioned above the plate element. One or more spring elements may be positioned between the plate element and the first region of the bottom surface of the heat sink. The one or more spring elements may be under a compressive load between the plate element and the heat sink. One or more thermal conduit elements may be secured to both the plate element and the heat sink. The one or more thermal conduit elements may apply at least a part of the compressive load between the plate element and the heat sink.

Abstract: The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.

Abstract: An image sensor may include a substrate having a first surface and a second surface on opposite sides, a first transistor having a first gate disposed on the first surface, a photoelectric conversion layer which generates photocharges from light incident in a first direction, a second transistor having a transistor structure disposed between the first surface and the photoelectric conversion layer and spaced from the photoelectric conversion layer, and includes a semiconductor layer composed of a metal oxide semiconductor material. The semiconductor layer may have a third surface facing the first direction and a fourth surface opposite the third surface, with a second gate disposed on the semiconductor layer. The semiconductor layer may be connected to the first gate. A light blocking layer may be disposed between the third surface and the photoelectric conversion layer, and spaced from the photoelectric conversion layer.

Abstract: A displacement magnification device has a first link portion including a first rigid body and a first plate spring that couples the first rigid body to a supporting portion and a movable portion. A second link portion includes a second rigid body and a second plate spring that couples the second rigid body to the supporting portion and the movable portion. In this structure, the first rigid body and the second rigid body play roles to suppress the bending of the first plate spring and the second plate spring. In addition, a connection portion between the first plate spring and the supporting portion, a connection portion between the second plate spring and the supporting portion, a connection portion between the first plate spring and the movable portion, and a connection portion between the second plate spring and the movable portion play roles of elastic hinges.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A germanium-on-silicon avalanche photodetector includes a silicon device layer of a silicon-on-insulator substrate having a central region characterized by modest-heavy n+ doping state between a first electrode region and a second electrode region in heavy n++ doping state; a first sub-layer of the central region modified to nearly neutral doping state and located from a first depth down to a second depth below a top surface of the silicon device layer; a second sub-layer of the central region modified to modest p doping state embedded from the top surface down to the first depth to interface with the first sub-layer; a layer of germanium with a bottom side attached to the top surface of the second sub-layer; and a third sub-layer embedded into a top side of the layer of germanium, characterized by heavy p++ doping state.

Abstract: An integrated circuit is provided. The integrated circuit includes a first trace, a second trace and a third trace. The first trace, the second trace and the third trace are each a continuous trace. The first trace, the second trace and the third trace together use only two conductor layers of a semiconductor structure. In a crossing area of the first trace, the second trace and the third trace, the first trace crosses the second trace once, the first trace crosses the third trace once, and the second trace crosses the third trace once.

Abstract: A semiconductor device includes a semiconductor chip including a substrate and a MEMS element, wherein the substrate includes a surface, and wherein the MEMS element is disposed at the surface of the substrate and the MEMS element includes a sensitive area; a first electrical interconnect structure electrically connected to the surface of the substrate; a carrier electrically connected to the first electrical interconnect structure; and a first stress relieve spring entrenched in the carrier, wherein the first stress relieve spring is a single integral channel that comprises two parallel channels that join together at a periphery of the first electrical interconnect structure to form the single integral channel that wraps around a portion of the periphery of the first electrical interconnect structure, wherein the two parallel channels extend outward, in parallel, from the periphery of the first electrical interconnect structure to a first termination region of the carrier.

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

Abstract: An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: An organic device comprising a reflective electrode, an organic layer arranged on the reflective electrode, a semi-transmissive electrode arranged on the organic layer and a reflection surface formed above the semi-transmissive electrode is provided. The organic layer emits white light and includes a blue-emitting layer. An optical distance L of the organic layer satisfies L?[{(?r+?s)/?}×(?b/4)]×1.2, where ?b is a peak wavelength of the blue-emitting layer, ?r and ?s are a phase shift of the wavelength ?b in the reflective electrode and the semi-transmissive electrode, respectively. A resonant wavelength of an optical distance between the semi-transmissive electrode and the reflection surface is shorter than the wavelength ?b.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

Abstract: A ferromagnetic laminated film includes a plurality of first magnetic layers, at least one second magnetic layer, and at least one first non-magnetic layer, in which the first magnetic layers are alternately laminated with the second magnetic layer or the first non-magnetic layer, and a material forming the first magnetic layers is different from a material forming the second magnetic layer, and the first magnetic layers, the first non-magnetic layer, and the second magnetic layer are a material combination in which interface magnetic anisotropy is generated between the first magnetic layer and the first non-magnetic layer, and a material combination in which interface magnetic anisotropy is generated between the first magnetic layer and the second magnetic layer.