Abstract: A method for manufacturing a semiconductor device including forming a temporary fixing laminated body including a carrier, and a sealing structure body provided on a main surface of the carrier and including a plurality of semiconductor chips and a sealing portion sealing the plurality of semiconductor chips, and removing the carrier from the temporary fixing laminated body. The semiconductor chip includes a chip main body including a first surface and a second surface, and a connection terminal provided on the first surface. The sealing portion includes an integrated protective layer adjacent to the carrier in the temporary fixing laminated body, covering the second surface. The protective layer is a cured curable resin film. The protective layer and the carrier are separated by irradiating the temporary fixing laminated body with incoherent light to remove the carrier from the temporary fixing laminated body.

Abstract: In one example, a semiconductor device includes a substrate. The substrate includes a base including a top side and a cavity side opposite to the top side, leads extending from the cavity side, and an encapsulant interposed between the leads. An electronic component is located on the cavity side and spaced apart from the encapsulant. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

Abstract: A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first-conduction-type well region formed on a surface portion of the main surface of the semiconductor layer; a second-conduction-type first region formed on a surface portion of the well region; a second-conduction-type second region formed on the surface portion of the well region at an interval from the first region; a first-conduction-type diffusion layer formed on the surface portion of the main surface adjacent to the first region; a planar gate structure formed on the main surface of the semiconductor layer to face a first-conduction-type channel region between the first region and the second region; and a memory structure including a charge storage film arranged adjacent to a lateral side of the planar gate structure on a side of the first region.

Abstract: An embodiment memory device includes a drain electrode disposed on a semiconductor substrate, a channel region in contact with the drain electrode, a source electrode in contact with the channel region, and a floating gate region in contact with the source electrode and the drain electrode, the floating gate region including a nano-dot region including at least one nano-dot gate, wherein the drain electrode is overlapped with the nano-dot region, and wherein the nano-dot region is overlapped with the channel region.

Abstract: A method for manufacturing an optoelectronic device using halide perovskite layers includes providing a substrate; optionally depositing a first spacer layer on the substrate; depositing a first emission layer on the first spacer layer, if present, or on the substrate; depositing a second spacer layer on the first emission layer, depositing a second emission layer on the second spacer layer; optionally depositing a third spacer layer on the second emission layer; optionally depositing a third emission layer on the third spacer layer, if present; optionally depositing a fourth spacer layer on the third emission layer, if present; wherein the first emission layer, the second emission layer, and the third emission layer comprise a halide perovskite layer, and wherein the halide perovskite layer of the first emission layer, the second emission layer, and the third emission layer each comprises a three-dimensional halide perovskite, a two-dimensional halide perovskite, or a combination thereof.

Abstract: A semiconductor device includes a first electrode, a second electrode located on the first electrode, a semiconductor part located between the first electrode and the second electrode, a first interconnect located between the semiconductor part and the second electrode, a third electrode located in the semiconductor part and separated from the semiconductor part, a fourth electrode located lower than the third electrode in the semiconductor part, a first plug connecting the second electrode to the fourth electrode, and a second plug. The third electrode includes a ring portion, and an extension portion extending from the ring portion into an interior of the ring portion. The fourth electrode is located in the interior of the ring portion in a plane perpendicular to a vertical direction. The fourth electrode is separated from the semiconductor part. The second plug connects the first interconnect to the extension portion.

Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes: a first conductivity type nitride semiconductor layer; a V-pit generation layer disposed on the n-type nitride semiconductor layer and having a V-pit; a lower active layer disposed on the V-pit generation layer; an upper active layer disposed on the lower active layer; an intermediate layer disposed between the lower active layer and the upper active layer; a second conductivity type nitride semiconductor layer disposed on the upper active layer, an upper step coverage layer disposed between the second conductivity type semiconductor layer and the upper active layer; and a lower step coverage layer disposed between the intermediate layer and the lower active layer, in which in an electroluminescence spectrum, the light emitting diode emits light having a highest peak intensity in a wavelength range of 500 nm or more in a visible light region.

Abstract: A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

Abstract: An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to e-fuse structures and methods of manufacture. The structure includes: a silicided fuse structure which includes a narrow portion and wider, end portions; dummy structures on opposing sides of the silicided fuse structure; and sidewall spacer material separating the dummy structures from the silicided fuse structure.

Abstract: Disclosed is a 3-terminal neuromorphic synaptic device including a substrate, a source electrode and a drain electrode provided on the substrate to be spaced apart from each other, a channel area provided on the substrate to be electrically connected to the source electrode and the drain electrode, between the source electrode and the drain electrode, an ion transport layer provided on the channel area, a gate electrode provided on the ion transport layer, and a voltage application part that applies a gate voltage to the gate electrode. The gate electrode is formed of at least one of an oxide-based material including mobile ions, a chalcogenide-based material including the mobile ions, and a nitride-based material including the mobile ions.

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein that has a graded content to reduce the coefficient of thermal expansion at the backside surface of the integrated circuit device. The filler material may have at least two filler material particle constituents having different particle diameters, wherein a first filler material particle constituent that has the smaller average diameter is closest to the backside surface of the integrated circuit device and wherein a second filler material constituent that has the larger average diameter is farthest from the backside surface of the integrated circuit device.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate containing oxygen. An oxygen concentration distribution in a depth direction of the semiconductor substrate has a high oxygen concentration part where an oxygen concentration is higher on a further upper surface-side than a center in the depth direction of the semiconductor substrate than in a lower surface of the semiconductor substrate. The high oxygen concentration part may have a concentration peak in the oxygen concentration distribution. A crystal defect density distribution in the depth direction of the semiconductor substrate has an upper surface-side density peak on the upper surface-side of the semiconductor substrate, and the upper surface-side density peak may be arranged within a depth range in which the oxygen concentration is equal to or greater than 50% of a peak value of the concentration peak.

Abstract: A split in a dicing street in a semiconductor film is prevented. A semiconductor device includes: a first dicing street passing between a plurality of element regions on which a plurality of protective films are formed one-to-one, the first dicing street extending along a first axis; a second dicing street passing between the plurality of element regions and extending along a second axis; and a stop island disposed on the upper surface of the semiconductor film at an intersection between the first dicing street and the second dicing street, the stop island being in non-contact with the plurality of element regions. X_si>X_ds and Y_si<Y_ds are satisfied.

Abstract: Methods and apparatus for forming an integrated circuit structure, comprising: delivering a process gas to a process volume of a process chamber; applying low frequency RF power to an electrode formed from a high secondary electron emission coefficient material disposed in the process volume; generating a plasma comprising ions in the process volume; bombarding the electrode with the ions to cause the electrode to emit electrons and form an electron beam; and contacting a dielectric material with the electron beam to cure the dielectric material, wherein the dielectric material is a flowable chemical vapor deposition product. In embodiments, the curing stabilizes the dielectric material by reducing the oxygen content and increasing the nitrogen content of the dielectric material.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.

Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an e-fuse with metal fill structures and methods of manufacture. The structure includes: an insulator material; an e-fuse structure on the insulator material; a plurality of heaters on the insulator material and positioned on sides of the e-fuse structure; and conductive fill material within a space between the e-fuse structure and the plurality of heaters.