Abstract: A semiconductor element includes a main body and an obverse face electrode. The main body includes an obverse face that faces in a thickness direction. The obverse face electrode is electrically connected to the main body. The obverse face electrode includes a first section and a plurality of second sections. The first section is provided on the obverse face. The plurality of second sections are in contact with the first section, and spaced apart from each other in a direction perpendicular to the thickness direction. A total area of the plurality of second sections is smaller than an area of the first section including portions overlapping with the plurality of second sections, in a view along the thickness direction.

Abstract: Provided is a display device including an organic insulating layer; a pixel electrode on the organic insulating layer; a pixel defining layer configured to cover an edge of the pixel electrode, having an opening corresponding to the pixel electrode, the pixel defining layer including a first layer including an inorganic insulating material and a second layer having less light transmittance in a first wavelength band than the first layer; an intermediate layer on a portion of the pixel electrode exposed via the opening, and including an emission layer; and an opposite electrode on the intermediate layer.

Abstract: A semiconductor device includes a metal plate; a sidewall member surrounding a periphery of a space above the metal plate; a circuit board provided on the metal plate; a semiconductor chip provided on the circuit board; a first wire connecting the semiconductor chip and an interconnect part of the circuit board; a first resin member covering a bonding portion between the semiconductor chip and the first wire; and a second resin member provided in the space, the second resin member covering an upper surface of the metal plate, the circuit board, the first resin member, and the first wire. A Young's modulus of the first resin member is greater than a Young's modulus of the second resin member. A volume of the second resin member is greater than a volume of the first resin member.

Abstract: A method for producing a plurality of radiation emitting semiconductor devices and a radiation emitting semiconductor device are disclosed. In an embodiment a method include providing an auxiliary carrier, applying a plurality of radiation-emitting semiconductor chips to the auxiliary carrier with front sides so that rear sides of the semiconductor chips are freely accessible, wherein each rear side of the respective semiconductor chip has at least one electrical contact, applying spacers to the auxiliary carrier so that the spacers directly adjoin side surfaces of the semiconductor chips and applying a casting compound between the semiconductor chips by a screen printing process such that a semiconductor chip assembly is formed, wherein a screen for the screen printing process has a plurality of cover elements, and wherein each cover element covers at least one electrical contact.

Abstract: A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.

Abstract: The present disclosure concerns a mounting device for semiconductor packages, and a heat dissipation assembly with such a mounting device. The mounting device includes a bottom side comprising one or more cavities to house semiconductor packages, and a top side comprising a plurality of holes extending from the bottom side to the top side for accommodating contact pins of the semiconductor packages. A fixation mechanism fixes the mounting device to a heat dissipation structure.

Abstract: An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW2N).

Abstract: An imaging device including: a semiconductor substrate having a first and second surface opposite to the first surface; a microlens located closer to the first surface than the second surface; a first photoelectric converter located between the first surface and the microlens, where the first photoelectric converter includes a first electrode, a second electrode, and a photoelectric conversion layer that is located between the first electrode and the second electrode and that converts light into electric charges; and a signal detecting section located in the semiconductor substrate, the signal detecting section being configured to output a signal corresponding to the electric charges. The first photoelectric converter is the closest of any photoelectric converter existing between the first surface and the microlens to the first surface, and a focal point of the microlens is located below a lowermost surface of the photoelectric conversion layer and above the signal detecting section.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate, an insulating layer, a first crack stopper, and a first crack detection line. The base substrate includes a display region and a non-display region. The insulating layer is located on the base substrate. The first crack stopper is located in the non-display region and is configured to block the first crack in the insulating layer from extending towards the display region. The first crack detection line is located in the non-display region, an edge of the orthographic projection of the first crack stopper on the base substrate close to the display region is a blocking edge, and the orthographic projection of the first crack detection line on the base substrate is located at a side of the orthographic projection of the first crack stopper on the base substrate away from the blocking edge.

Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting assembly having a first light emitting diode package structure and a second light emitting diode package structure. The light emitting assembly can generate a mixed light source having a spectral deviation index. The first light emitting diode package structure can generate a first light source having a first spectral deviation index. The second light emitting diode package structure can generate a second light source having a second spectral deviation index. When the first light source and the second light source are within a range from 460 to 500 nm, a sum of the first spectral deviation index and the second spectral deviation index is within a range from ?0.3 to 0.3, and a difference between the first spectral deviation index and the second spectral deviation index is at least greater than 0.2.

Abstract: A semiconductor structure, a method for producing a semiconductor structure and a light emitting device are disclosed. In an embodiment a semiconductor structure includes a plurality of discrete encapsulated semiconductor nanoparticles and a plurality of discrete semiconductor free nanoparticles, wherein the discrete encapsulated semiconductor nanoparticles and the discrete semiconductor free nanoparticles form an agglomerate.

Abstract: An embodiment includes a semiconductor device including a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulation layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed on the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; a second cover electrode disposed on the second electrode; and a second insulation layer extending from an upper surface of the first cover electrode to an upper surface of the second cover electrode.

Abstract: The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a first electrode layer on the base substrate and including a plurality of first electrodes respectively in the plurality of subpixel areas; an auxiliary electrode layer; and an insulating layer between the first electrode layer and the auxiliary electrode layer. The first electrode layer and the auxiliary electrode layer are spaced apart and insulated from each other by the insulating layer. An orthographic projection of each individual one of the plurality of first electrodes on the base substrate at least partially overlap with an orthographic projection of the auxiliary electrode layer on the base substrate. Each of the plurality of first electrodes is electrically connected to a pixel circuit configured to drive light emission in a respective one of the plurality of subpixel areas.

Abstract: The present disclosure is related to a light emitting diode. The light emitting diode may include a pixel unit which may include a first sub-pixel. The first sub-pixel may include a dummy electrode layer and a first electrode layer on the dummy electrode layer. The dummy electrode layer may include a first reflective layer. The first electrode layer may include a second reflective layer and a second transparent conductive layer on the second reflective layer.

Abstract: A display panel is provided, including a substrate and an organic light-emitting component disposed on the substrate. The display panel further includes a planarization layer and an insulation layer disposed on the planarization layer. An anode of the organic light-emitting component is disposed on the planarization layer. The insulation layer is disposed on the planarization layer and configured to cover the planarization layer, and the anode of the organic light-emitting component is exposed through the insulation layer.

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.