Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.

Abstract: It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 ?m or more). Thus, it is a further object of the invention to reduce defects caused by the unevenness due to the contact hole. It is a feature of the invention to form a wiring by filling the contact hole with conductive fine particles. The conductive fine particles can be easily dispersed into a wiring material by using conductive fine particles having high wettability with the wiring material, thereby making a contact. Thus, planarization of a contact hole can be achieved without performing a reflow process. Further, more planarity can be obtained by performing a reflow process in addition, and the reliability is improved accordingly.

Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.

Abstract: In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and has conductive traces formed thereon. A soldermask is received on the one side, and has a plurality of openings formed therethrough to locations on the conductive traces. The soldermask includes a peripheral elongated trench therein positioned on the one side to align with at least a portion of an elongated mold void perimeter of a transfer mold to be used for transfer mold packaging of the one side. In one implementation, the invention includes a transfer mold semiconductor packaging process. In one implementation, the invention includes a semiconductor package. In one implementation, the invention includes a ball grid array.

Abstract: With respect to a work obtained by joining a semiconductor wafer and a supporting member to each other via a both-faced adhesive sheet having heating separability, the surface of the supporting member is suction-held at a suction stage and is heated, thereby making the adhesive strength of an adhesive layer almost disappear. A Bernoulli chuck is moved close from the back side of the semiconductor wafer to separate the semiconductor wafer in a non-contact manner and to suspension-hold the semiconductor wafer in a state where the semiconductor wafer floats in the air.

Abstract: A method for manufacturing a vertical cavity surface emitting laser formed by laminating a plurality of layers on a substrate, includes coupling two layers of the plurality of layers by joining at room temperature or joining while heating.

Abstract: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: A CMOS image sensor and method for fabricating the same is disclosed that reconditions, repairs and/or protects a surface of a photodiode area and improves characteristics of the image sensor. The method includes forming a photodiode area and a plurality of transistors, implanting a predetermined ion into a surface of the photodiode area, and forming a surface oxide film on the surface of the photodiode area by oxidation. Therefore, it is possible to recover or repair the photodiode surface damaged during various fabrication processes, reduce or minimize surface leakage of the photodiode during subsequent processes, and improve image sensor characteristics by increasing incident light on the photodiode.

Abstract: Provided is a method of fabricating a semiconductor optical device for use in a subscriber or a wavelength division multiplexing (WDM) optical communication system, in which a laser diode (LD) and a semiconductor optical amplifier (SOA) are integrated in a single active layer. The laser diode (LD) and the semiconductor optical amplifier (SOA) are optically connected to each other, and electrically insulated from each other by ion injection, whereby light generated from the LD is amplified by the SOA to provide low oscillation start current and high intensity of output light when current is individually injected through each electrode.

Abstract: An insulating film comprising an organic silicon material having a C—Si bond and a Si—O bond is used for a semiconductor integrated circuit, and for polishing of its surface, a polishing compound comprising water and particles of at least one specific rare earth compound selected from the group consisting of a rare earth oxide, a rare earth fluoride, a rare earth oxyfluoride, a rare earth oxide except cerium oxide and a composite compound thereof, or a polishing compound having the above composition and further containing cerium oxide particles, is used. It is possible to provide a high quality polished surface which is free from or has reduced defects such as cracks, scratches or film peeling.

Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.

Abstract: A thin-film structural body formed by using a semiconductor processing technique and a manufacturing method thereof, and particularly a thin-film structural body constituting a semiconductor acceleration sensor and a manufacturing method thereof. The thin-film structural body allows the thin-film member to be easily stress-controlled, and easily makes the film-thickness of the thin-film member thicker. The thin-film member forms a mass body and, beams and fixed electrodes of the semiconductor acceleration sensor are constituted by a plurality of doped polysilicon thin-films that are laminated by performing a step of film deposition of polysilicon while, for example, phosphorous is being doped as impurities plural times.

Abstract: A method supports, on a printed circuit board, a circuit package including a substrate having a solder column array. The method comprises providing the circuit package with an over-sized lid that extends outwardly over an edge of the substrate. The circuit package is electrically connected to the printed circuit board via the solder column array and a plurality of supports are secured to the printed circuit board in position underneath the lid of the circuit package while leaving a gap between the lid and the support. A static compressive force is applied and maintained to the circuit package relative to the printed circuit board, thereby causing the solder column array to creep until the gap is closed and a substantial portion of the compressive force is borne by the supports.

Abstract: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: One embodiment of this invention pertains to multiple encapsulated thin-film electronic devices. These encapsulated devices include a substrate and multiple thin-film electronic devices are on this substrate. Each of the multiple thin-film electronic devices has an active area. The encapsulated devices also include an encapsulation layer that is on the substrate and this encapsulation layer has multiple holes and these multiple holes are over the active areas of the multiple thin-film electronic devices. The encapsulated devices also include multiple substantially flat encapsulation pieces that are on the encapsulation layer and these multiple substantially flat encapsulation pieces cover the multiple holes of the encapsulation layer. An absorbent material is not attached to any of the substantially flat encapsulation pieces.

Abstract: A method of fabricating a CMOS image sensor can minimize a dark current by avoiding a dry etch process of a photodiode surface. The method can also reduce a contact resistance and variation of the contact resistance of a read-out circuit unit within a unit pixel. The method includes steps of forming an insulating layer on a semiconductor substrate divided into a photodiode area and a transistor area, removing the insulating layer on a gate electrode forming area, forming a gate insulating layer, forming a conductive layer, forming a gate electrode by planarizing the conductive layer, selectively removing the insulating layer to expose the semiconductor substrate, forming a lightly doped impurity region in the exposed semiconductor substrate, forming a spacer on a sidewall of the gate electrode, completely removing the insulating layer, and forming a heavily doped impurity region on the transistor area of the semiconductor substrate.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.