Abstract: An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion adjacent to the groove; and a circuit element formed between the electrodes. An electrode is also formed on the opposing side faces of said substrate at a portion other than the grooves. This structure enables to improve the reliability of a soldered portion even for small electronic components with about 10 &mgr;m thick electrodes such as chip resistors, chip capacitors, and chip inductors.

Abstract: A circuit board includes an electrical insulator layer formed of a reinforcer sheet with density distribution in its in-plane direction, an electrical conductor filled in a plurality of inner via holes provided in the electrical insulator layer in its thickness direction, and a wiring layer connected to the electrical conductor. The inner via holes provided in a high-density portion of the reinforcer sheet are formed to have a smaller cross-section than the inner via holes provided in a low-density portion of the reinforcer sheet. In this manner, it is possible to provide a circuit board that can achieve a high-density wiring and an inner via connection resistance with less variation, when a base material including a reinforcer sheet with density distribution in its in-plane direction such as a glass-epoxy base material is used for an insulator layer.

Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0˜2.0 mass %, In: 0.1˜10 mass %, and Sn: remaining amount.

Abstract: A method of manufacturing a multilayer wiring board comprising a step of forming an upper wiring layer (27), a part thereof being electrically connected to a pillar-shaped metallic body (24a), after he pillar-shaped metal body (24a) is formed on a lower wiring layer (22) is characterized in that the step of forming the metallic body includes a sub-step of forming a plating layer (24) constituting the metallic body, a sub-step of forming a mask layer (25) on the surface where the metal body is formed, of the plating layer, and a sub-step of etching the plating layer. The manufacture can be carried out with simple equipment combination of conventional steps and the wiring layer can be made fine.

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract: A printed circuit board comprises a base substrate including a conductive circuit pattern on a top surface thereof, and at least one photosensitive resin layer positioned on the base substrate. The resin layer exposure is performed through a photomask having light-shielding and exposure amount adjusting portions as part thereof to accommodate for varying resin layer thicknesses.

Abstract: An epoxy/clay nanocomposite suitable for use as matrix material for printed circuit boards is disclosed. The nanocomposite of the present invention comprises a layered clay material uniformly dispersed in an epoxy polymer matrix, wherein the clay material has been modified to an organoclay by ion exchange with (1) benzalkonium chloride and (2) dicyandiamide or tetraethylenepentamine. The epoxy/clay nanocomposites of the present invention have superior dimensional and thermal stability, and a lower hygroscopic property. The invention also includes the prepregs or circuit boards containing the epoxy/clay nanocomposite.

Abstract: A polyimide film is produced by copolymerizing pyromellitic dianhydride in combination with phenylenediamine, methylenedianiline and 3,4′-oxydianiline in a specific molar ratio. The polyimide film, when used as a metal interconnect board substrate in flexible circuits, chip scale packages (CSP), ball grid arrays (BGA) or tape-automated bonding (TAB) tape by providing metal interconnects on the surface thereof, achieves a good balance between a high elastic modulus, a low thermal expansion coefficient, alkali etchability and film formability.

Abstract: A composite material for use in making printed wiring boards comprising a carrier having releasable conductive fine particles on its surface. The composite is laminated to a substrate with the conductive fine particles facing the substrate and the carrier removed, leaving the surface of the conductive fine particles exposed. Printed wiring is formed using the conductive fine particles as its base, thus providing improved peel strength and permitting formation of fine wiring lines and spaces.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: There is disclosed a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein Erratic phenomenon does not occur in a MOS device fabricated on the silicon epitaxial wafer, a silicon epitaxial wafer having oxide dielectric breakdown voltage of 20 MV/cm or more, a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 1×1017 to 1×1018 atoms/cm3 or 5×1016 to 5×1017 atoms/cm3, a method for producing a silicon epitaxial wafer comprising subjecting a silicon wafer to heat treatment in a hydrogen atmosphere, and then growing an epitaxial layer on the silicon wafer wherein the initial oxygen concentration of the silicon wafer, the heat treatment temperature and the heat treatment time of the heat treatment are predetermined so that oxygen concentration at an interface between the epitaxial layer and the silicon w

Abstract: A multi-layer printed circuit board includes a via having a conductive upper portion, a conductive lower portion, and an electrically insulating intermediate portion between the upper and lower portions. In one embodiment, the insulating intermediate portion of the via is provided by a non-platable layer of the circuit board, as may be comprised of PTFE. Vias having a continuous conductive coating may be formed through clearance holes in the non-platable layer which are provided with a platable inner surface, either by filling the hole with a platable material, such as epoxy resin, prior to laminating the board or by chemically conditioning the non-platable material to make it platable. In a further embodiment, the as insulating intermediate portion of the via has a narrower diameter than the conductive upper and lower portions.

Abstract: A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Abstract: A crystallized glass composition contains a principal ingredient comprising SiO2, MgO and Al2O3 and contains about 2 to 20 parts by weight of B2O3 relative to 100 parts by weight of the principal ingredient. In a ternary diagram, the weight ratio (SiO2, MgO, Al2O3) lies within a region surrounded by point A (44.0, 55.0, 1.0), point B (34.5, 64.5, 1.0), point C (35.0, 30.0, 35.0) and point D (44.5, 30.0, 25.5).

Abstract: This invention concerns electronic substrates comprising a non-woven filler material and a resin material. The present invention also includes electronic products manufactured from the electronic substrates of this invention including, but not limited to prepregs, metal clad laminates, and printed wiring boards with and without lased via holes. The present invention further includes a method of manufacturing printed built-up wiring boards including the steps of forming a prepreg and forming at least one via in the prepreg.

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: A ceramic green sheet is formed from a ceramic slurry composition comprising a ceramic powder such as BaTiO3, a vehicle in the state of emulsion in which an organic binder consisting of polyurethane resin particles having an average particle size of about 120 nm or less is dispersed in an aqueous solvent, and a surfactant comprising an alkyne glycol having one or more triple bonds in its molecule and/or an ethylene oxide addition product of such an alkyne glycol. A very thin aqueous ceramic green sheet is provided that is free from pin holes, and has low surface roughness, high tensile strength and high elongation.

Abstract: The present invention relates to the fabrication process for the printed wiring boards and flex circuits. An electrostatic printing plate includes a substrate with an image receiving layer applied thereto. The image receiving layer is a toner with a metallic toner and subsequently fixed in place or is transferred to a layer. The metal toner is then fixed on this receiving surface.

Abstract: A chip carrier for accommodating a passive component is proposed, allowing at least a chip to be electrically connected to the chip carrier. At least a pair of spaced-apart solder pads are formed on the chip carrier in no interference with the electrical connection between the chip and the chip carrier. A passive component is bonded at its two ends onto the solder pads by solder paste that electrically connects the passive component to the chip carrier. A recessed portion formed between the pair of the solder pads, is associated with a bottom surface of the passive component to form a passage, allowing a resin material for encapsulating the passive component or the chip to pass through and fill the passage, whereby the filled passage can prevent bridging of the solder paste and short circuit of the passive component from occurrence, thereby making yield of fabricated products desirably improved.

Abstract: The present invention is a persulfate etchant composition especially useful for dissolving copper during fabrication of microelectronic packages. The etchant is characterized by its ability to selectively etch copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this etchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate etchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 230 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.