Patents Examined by Cathy Lam
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Patent number: 6717218Abstract: A contact hole is formed, by etching that uses buffered hydrofluoric acid, in a gate insulating film made of SiO2 and an interlayer insulating layer, formed on the gate insulating film, which is made of SiN. In this contact hole, there is formed an electrode which includes: a first protective metal layer made of a refractory metal; a wiring layer, formed on the first protective metal layer, which is made of a metal whose resistance is lower than that of the refractory metal; and a second protective metal layer, made of a refractory metal, which is formed thicker than the gate insulating film.Type: GrantFiled: March 5, 2003Date of Patent: April 6, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Isao Hasegawa, Koji Suzuki
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Patent number: 6717262Abstract: A mounted circuit substrate has at least one conductive layer. The side faces of a component mounting pad is formed on a surface of the substrate, and includes at least a columnar pattern made of a metal highly resistant to erosion by solder The side faces of the component mounting pad are completely covered with an organic insulating layer. Therefore, the component mounting pad can withstand molten solder stresses accompanying component replacement even when component replacement is done many times.Type: GrantFiled: November 6, 2000Date of Patent: April 6, 2004Assignee: Fujitsu LimitedInventors: Kiyokazu Moriizumi, Manabu Watanabe
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Patent number: 6717794Abstract: A composite multilayered ceramic board includes a multilayered ceramic board made of dielectric ceramics, a multilayered ceramic board made of magnetic ceramics and an adhesive layer made of thermosetting resin such as polyimide and the like. In this composite multilayered ceramic board, the dielectric multilayered ceramic board and the magnetic multilayered ceramic board are joined through the adhesive layer.Type: GrantFiled: December 28, 2001Date of Patent: April 6, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hideki Yoshikawa, Seiichirou Takahashi
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Patent number: 6713163Abstract: A fire retardant multilayered printed wiring board without halogen compounds, having enhanced thermal conductivity of insulator layers to prevent electronic components from being damaged during soldering. The insulator layers are formed of a glass cloth impregnated with an epoxy resin composition. Metal foil layers, in each of which a circuit is formed, are laminated alternately with the insulator layers. The epoxy resin composition includes at least phosphate ester, aluminum hydroxide, silica, calcium oxide, strontium titanate, and iron oxide. Inorganic components are provided in the insulator layers as about 8% to about 18% by mass of P2O5, about 20% to about 28% by mass of Al2O3, about 0.1% to about 0.6% by mass of SiO2, about 0.1% to about 1.0% by mass of Cl, about 15% to about 20% by mass of CaO, about 0.3% to about 0.5% by mass of TiO2, about 0.2% to about 0.4% by mass of Fe2O3, and about 0.1% to about 0.3% by mass of SrO, in converted values as measured by an X-ray fluorescence analysis.Type: GrantFiled: December 31, 2002Date of Patent: March 30, 2004Assignee: Fuji Electric Co., Ltd.Inventor: Shigemasa Saito
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Patent number: 6713873Abstract: The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal. The present invention also discloses a structure including: a substrate; a first interlayer dielectric located over the substrate; a first adhesion promoter layer located over the first interlayer dielectric; an etch stop layer located over the first adhesion promoter layer; a second adhesion promoter layer located over the etch stop layer; and a second interlayer dielectric located over the second adhesion promoter layer.Type: GrantFiled: November 27, 2002Date of Patent: March 30, 2004Assignee: Intel CorporationInventors: Jennifer O'Loughlin, Andrew W. Ott, Bruce J. Tufts
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Patent number: 6709606Abstract: An anisotropic conductive film 1 comprising an insulating film 2 and plural conductive paths (3, 4), wherein the plural conductive paths are insulated from each other and penetrate the insulating film 2 in the thickness direction of the film, with both ends of the paths being exposed on both surfaces of the insulating film, and wherein a conductive path 3 capable of contact with an electrode 12 of a semiconductor element 11 and a circuit 14 of a circuit board 13 has at least one end protruding more than an end on the same side of a conductive path incapable of contact with the electrode and the circuit. The ACF of the present invention can prevent a conductive path not involved in electrical connection from being in contact with a part other than an electrode of a semiconductor element and/or a part other than a circuit of a circuit board.Type: GrantFiled: April 17, 2002Date of Patent: March 23, 2004Assignee: Nitto Denko CorporationInventors: Akiko Matsumura, Miho Yamaguchi, Yuji Hotta
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Patent number: 6706374Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.Type: GrantFiled: November 21, 2002Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, James M. Ocker, Rick A. Leininger
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Patent number: 6704189Abstract: A multilayer ceramic capacitor with external terminals having terminal electrodes and external terminals of the electronic device body electrically bonded through a solder layer, wherein the solder layer is comprised of an Sn—Sb high temperature lead-free solder, the ratio between the Sn and Sb in this solder layer is, by ratio by weight percent, in a range of Sn/Sb=70/30 to 90/10, and the solder layer and terminal electrodes are formed between them with a diffusion layer formed by diffusion of a conductive ingredient of the terminal electrodes into the solder layer.Type: GrantFiled: April 2, 2003Date of Patent: March 9, 2004Assignee: TDK CorporationInventors: Akitoshi Yoshii, Kazuhiko Kikuchi, Takashi Kamiya, Hiromi Kikuchi
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Patent number: 6703105Abstract: A stereolithographically fabricated marking for a semiconductor device component, such as a packaged or unpackaged semiconductor device or another substrate. When formed on a semiconductor device with a stereolithographically formed package structure, the marking may be integral with the package. The marking may be formed as apertures through or recesses in one or more stereolithographically fabricated layers of material, or the marking may include one or more stereolithographically fabricated layers that protrude from a surface of a semiconductor device component. Raised markings may also be formed on the surfaces of packaged or bare semiconductor device components. Alternatively, the marking may be fabricated separately from a semiconductor device component, then secured thereto. Methods for stereolithographically marking semiconductor device components are also disclosed.Type: GrantFiled: November 21, 2002Date of Patent: March 9, 2004Assignee: Micron Technology, Inc.Inventors: Ford B. Grigg, James M. Ocker, Rick A. Leininger
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Patent number: 6703071Abstract: An absorbent article containing a composite mixture of absorbent macroporous particles and binder particles. Preferably, the absorbent macroporous particles are those having a macroporous structure which allow for the rapid flow of liquid therein, e.g., aerogels, xerogels, cryogels, or mixtures thereof. The absorbent articles produced thereby are preferably thin and lightweight, but maintain an ample rate of absorption allowing for a more rapid uptake of higher volumes of liquids.Type: GrantFiled: March 25, 2003Date of Patent: March 9, 2004Assignee: Koslow Technologies CorporationInventor: Evan E. Koslow
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Patent number: 6703114Abstract: In accordance with the present invention, there are provided novel assemblies which are useful for a variety of applications. Invention assemblies have low dielectric constant, making them suitable for use in a variety of electronic applications. In addition, invention assemblies are resistant to attack by acidic aqueous media, basic aqueous media and/or organic media, making it possible to subject such assemblies to a variety of processing conditions, such as, for example, chemical etching to introduce circuitry thereto.Type: GrantFiled: October 17, 2002Date of Patent: March 9, 2004Assignee: ArlonInventors: Chester Light Guiles, Scott Timon Allen, Ousama Najjar, William J. Bieschke
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Patent number: 6699571Abstract: Devices and methods for mounting components of electronic circuitry and these mounting devices are capable of surviving repeated thermal cycling. The devices comprise two metal laminate members brazed to a ceramic member on each of the two major surfaces of the ceramic member. The laminates preferably comprise a layer of molybdenum disposed between two layers of copper. The thickness of the individual layers comprising the metal laminate member may be varied to yield a laminate CTE similar to the CTE of the ceramic member to be joined.Type: GrantFiled: March 27, 2002Date of Patent: March 2, 2004Assignee: Morgan Advanced Ceramics, Inc.Inventor: John Antalek
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Patent number: 6700204Abstract: A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.Type: GrantFiled: January 2, 2002Date of Patent: March 2, 2004Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chien-Te Chen
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Patent number: 6698149Abstract: A decorative laminated building panel, usable for placement on an exterior surface of a building to improve the appearance thereof. The panel includes a foam core, a thin fabric mat attached to at least one surface of the foam core, and a durable material attached to the fabric mat with a binding agent. The durable material is intended to be used on an outward-facing surface of the panel, and may be selected from materials including stone, tile, and brick. Optionally, the panel may include a final finish covering the exposed exterior surface thereof, to give a more pleasing appearance. The panel is intended for a non load-bearing application, and the rear surface of the panel is preferred to be substantially cement-free, that is, free of Portland-type cement. Among other uses, panels according to the invention are suitable for use as exterior skirting material on manufactured homes.Type: GrantFiled: December 31, 2002Date of Patent: March 2, 2004Assignee: Paragon Building Systems, Inc.Inventor: Joseph L. Ruchgy
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Patent number: 6696163Abstract: A process for providing a metal-seeded liquid crystal polymer comprising the steps of providing a liquid crystal polymer substrate to be treated by applying an aqueous solution comprising an alkali metal hydroxide and a solubilizer as an etchant composition for the liquid crystal polymer substrate. Further treatment of the etched liquid crystal polymer substrate involves depositing an adherent metal layer on the etched liquid crystal polymer substrate. An adherent metal layer may be deposited using either electroless metal plating or vacuum deposition of metal such as by sputtering. When using electroless metal plating, a tin(II) solution applied to the liquid crystal polymer provides a treated liquid crystal polymer substrate to which the application of a palladium(II) solution provides the metal-seeded liquid crystal polymer. The etchant composition comprises a solution in water of from 35 wt. % to 55 wt. % of an alkali metal salt, and from 10 wt. % to 35 wt.Type: GrantFiled: March 7, 2002Date of Patent: February 24, 2004Assignee: 3M Innovative Properties CompanyInventor: Rui Yang
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Patent number: 6696139Abstract: A green sheet including a binder containing an acrylic resin having no polar group and a ceramics material in powder is prepared, and connection via are formed in the green sheet. Further, a conductor layer having virtually no voids is placed on the green sheet and a mask is also placed on the conductor layer. Then, the conductor layer is patterned by wet-etching so that wiring is formed thereon. A plurality of the green sheets thus formed are laminated, and a binding sheet, which contains an inorganic composition that has virtually no sintering shrinkage at the firing temperature of the multi-layered body as a main component, is formed on either both surfaces or one surface of the laminated body, and this is then fired, and thereafter, the binding sheet is removed.Type: GrantFiled: December 30, 2002Date of Patent: February 24, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Osamu Inoue, Junichi Kato
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Patent number: 6692818Abstract: A method for manufacturing a circuit board with high thermal dissipation includes the following steps: preparing a thermal conductive resin composition including 70 to 95 mass % of an inorganic filler and 5 to 30 mass % of a resin composition that includes a liquid thermosetting resin, a thermoplastic resin powder, and a latent curing agent; bonding the thermal conductive resin composition and a metal foil together by heating at a temperature lower than a temperature at which the thermosetting resin starts to cure while applying pressure so that the thermal conductive resin composition increases in viscosity and thus is solidified irreversibly; providing holes and curing the thermosetting resin to form an insulating substrate; and forming through holes and a circuit pattern. This method can achieve improved productivity and low cost in processing the holes. It is preferable that the thermal conductive resin composition is integral with a reinforcing material.Type: GrantFiled: June 5, 2002Date of Patent: February 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Hirano, Yoshihisa Yamashita, Seiichi Nakatani
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Patent number: 6692816Abstract: The invention provides abrasion resistant electrodes that comprise metal-coated conductive valleys between protrusions having a fractured metal coating thereon; the fractured metal coated protrusions are non-conductive. Electrical devices made from a plurality of said electrodes; and methods of making said devices.Type: GrantFiled: November 28, 2001Date of Patent: February 17, 2004Assignee: 3M Innovative Properties CompanyInventors: Paul D. Graham, Douglas A. Huntley
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Patent number: 6686029Abstract: A circuit board includes an electrical insulator layer formed of a reinforcer sheet with density distribution in its in-plane direction, an electrical conductor filled in a plurality of inner via holes provided in the electrical insulator layer in its thickness direction, and a wiring layer connected to the electrical conductor. The inner via holes provided in a high-density portion of the reinforcer sheet are formed to have a smaller cross-section than the inner via holes provided in a low-density portion of the reinforcer sheet. In this manner, it is possible to provide a circuit board that can achieve a high-density wiring and an inner via connection resistance with less variation, when a base material including a reinforcer sheet with density distribution in its in-plane direction such as a glass-epoxy base material is used for an insulator layer.Type: GrantFiled: February 24, 2003Date of Patent: February 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Suzuki, Toshihiro Nishii, Satoru Tomekawa, Fumio Echigo
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Patent number: 6683259Abstract: A single-sided circuit board uses two types a conventional, conductive ink and an enhanced conductive ink having to form cross-over connections. The conductive ink, enhanced ink, and an insulating overcoat layer are arranged in various configurations to minimize moisture and/or a positive electric field in the conductive ink that could cause migration of particles in the conductive ink.Type: GrantFiled: January 14, 2003Date of Patent: January 27, 2004Assignee: Siemens VDO Automotive CorporationInventor: Qi Tao