Patents Examined by Chameli Das
  • Patent number: 10810115
    Abstract: A computer device may include a memory configured to store instructions and a processor configured to execute the instructions to identify changes in source code of an application; generate a plurality of source code keywords based on the identified changes in the source code; and map the generated plurality of source code keywords to a plurality of testing keywords. The processor may be further configured to identify a plurality of test cases from a test cases database based on the plurality of testing keywords and inject the plurality of test cases into a testing queue of a testing system associated with the application. The computer device may further determine that the injected plurality of test cases sufficiently tested the changes in the source code and, based on the determining, update a deployed instance of the application to include the changes in the source code.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 20, 2020
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Nagaraju Manchiraju, Ravi K. Kotyala, Satya V. Nemana
  • Patent number: 10795666
    Abstract: Techniques to update a web application are described. A method includes receiving an application update request for a requested web application from a service worker web application executing in a web browser on a client device, the application update request comprising a cached version indicator for a local cached copy of the requested web application on the client device; determining whether an updated requested web application is available based on the cached version indicator. When the cached version indicator is less than a current version indicator, an archived copy of the previous version of the requested web application indicated by the cached version indicator and a current copy of the current version of the requested web application are retrieved, and a delta update is generated based on the archived copy and current copy. The delta update is sent to the service worker web application. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: October 6, 2020
    Assignee: WHATSAPP INC.
    Inventor: Matthew Ryan Anderson
  • Patent number: 10795646
    Abstract: The current document is directed to methods and systems that that generate proxy-object interfaces to external executable code for use in workflows executed by a workflow-execution system. The workflow-execution-engine component of a cloud-management system provides one example of a workflow-execution system in which proxy-object interfaces to external executable code are used. In one implementation, an existing automated-code-generation subsystem generates plug-in class declarations that represent one or more external executables. An additional class-wrapping subsystem then generates a proxy class for each code-generated plug-in class.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 6, 2020
    Assignee: VMware, Inc.
    Inventors: Vladimir Dimitrov, Julian Vassev
  • Patent number: 10783061
    Abstract: A method for testing a user interface includes determining states and state transitions associated with the user interface. A first plurality of states and a first plurality of state transitions of the user interface may be explored. A subset of a second plurality of states and a second plurality of state transitions of the user interface may also be explored. Paths that lead to cycles within the subset of the second plurality of states and the second plurality of state transitions may be penalized.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Parag Nandan Paul
  • Patent number: 10769045
    Abstract: A simulated attack service of a computing resource service provider generates a cloned computing resource environment on which a simulated attack is executed. The cloned computing resource environment may be based at least in part on a computing resource environment including a set of computing resources. The simulated attack service may execute the simulated attack by at least directing a simulated attack payload to the cloned computing resource environment based at least in part on a signature included in the simulated attack payload. A measure of the effectiveness of an intrusion detection system may then be generated based at least in part on threat analysis information generated by the intrusion detection system and the simulated attack payloads of the simulated attack.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 8, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Nima Sharifi Mehr
  • Patent number: 10754630
    Abstract: Systems, methods, and computer-readable media are described for selecting, at build time, a respective compiler and/or a respective set of compiler options for each section of code to be compiled such that the compiler/compiler options selected for each code section are optimized for that code section with respect to one or more metrics. Abstract syntax tree (AST) analysis and semantic analysis may be performed at build time for each section of code to identify the compiler/compiler options that produce compiled object code for that code section that maximizes or minimizes a desired metric. The metric according to which compiler/compiler option optimization is performed may be any suitable metric including, without limitation, performance, binary size, security, reliability, scalability, and so forth.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Strosaker, George C. Wilson, Nathan Fontenot, Christy L. Norman
  • Patent number: 10747510
    Abstract: Techniques to facilitate modifications to program execution in an application at runtime are disclosed herein. In at least one implementation, a copy of a code block associated with code is created. A flag associated with the copy of the code block is modified to mark the copy of the code block as having a native code version of the code. Metadata associated with the copy of the code block is modified to identify alternative code to run instead of the native code version of the code. A pointer associated with the code block is modified to point to a trampoline function. The trampoline function checks whether the code block is associated with a modification, and when the code block is associated with the modification, then the trampoline function calls the copy of the code block to invoke the alternative code by virtue of the flag and the metadata.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: August 18, 2020
    Assignee: Apptimize LLC
    Inventor: Timothy D. Lundeen
  • Patent number: 10740115
    Abstract: Structural identification of dynamically generated, pattern-instantiation classes may be utilized using structural descriptions. Instead of describing classes only by name, and using that name to locate that class, a class may be referred to by a generator function and arguments to the generator function. A structural description may specify the generator function and the parameters. In addition, a structural description of a class may be used as a parameter to a generator function specified by another structural description. A structural description may be used similarly to a class name for virtually any situation in which a class name may be used. Classes may be compared using their structural descriptions. For example, two structural descriptions may be considered to be the same class if they specify the same generator function and parameters.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 11, 2020
    Assignee: Oracle International Corporation
    Inventors: Brian Goetz, John R. Rose
  • Patent number: 10732963
    Abstract: An information handling system operating an automated UEFI variable update management system may comprise a processor executing machine-readable executable code instructions of the automated UEFI variable update management system to save to a memory and execute a first plurality of UEFI variables included in a first terse executable image, to receive a second terse executable image including a second plurality of UEFI variables in a second preset order, wherein each of the first plurality of UEFI variables and the second plurality of UEFI variables including a variable value, and a variable key pointing to a variable value location in the memory, to compare the first plurality of UEFI variables to the second plurality of UEFI variables, to retrieve from the first terse executable image and store in a variable update map the first plurality of UEFI variables, to retrieve from the second terse executable image and store in the variable update map the second plurality of UEFI variables, and to store the variable
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: August 4, 2020
    Assignee: Dell Products, LP
    Inventors: Michael W. Arms, Justin L. Frodsham
  • Patent number: 10733099
    Abstract: A method to minimize cache pressure using slot pressure profile (SPP)-guided Algorithm includes generating an intermediate SPP from a binary code of a DBMS. The generated intermediate SPP is received and a reference SPP is output. The reference SPP has a value assigned for each cache slot in a cache, whereby a cache slot value is indicative of cache pressure. The reference SPP is accepted and a candidate slot list related to the cache is produced by sorting the values in the reference SPP. A slot number among the candidate slot list is decided and passed to find an open memory address mapping to the decided slot number for a bee code, the bee code being a specialized version of a DBMS function created and loaded into the cache at run-time. A query with the bee code is executed using the open memory address found.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 4, 2020
    Assignees: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA, DATAWARE VENTURES, LLC
    Inventors: Richard T. Snodgrass, Saumya K. Debray, Rui Zhang, Yang Liu
  • Patent number: 10713144
    Abstract: The example embodiments are directed to a system and method for a virtual processor that enables real-time in situ disassembly and debugging. In one example, the method includes implementing a virtual processor in field programmable gate array (FPGA) programmable logic, the virtual processor comprising a virtual version of a target system, capturing data representative of operations in the virtual processor using a bus access device configured to provide direct access to components of the virtual processor, streaming the data to the embedded processor, storing the data in the memory device, and performing in-situ disassembly and debugging.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 14, 2020
    Assignee: General Electric Company
    Inventors: Andrew William Berner, Tab Mong, Richard Gawrelski
  • Patent number: 10713021
    Abstract: One embodiment provides for a computer-implemented method comprising receiving a request to compile a set of program instructions coded in a high-level language, the set of program instructions including a pointer to a virtual memory address, the pointer having a pointer encoding including a base address and a length; while compiling the set of program instructions, decoding the base address and length from the pointer, wherein the base address specifies a first boundary for a memory allocation, the length defines a second boundary for the memory allocation and the length is an encoding of a size of the memory allocation; and generating a set of compiled instructions which, when executed, enable access to a physical address associated with a virtual address between the first boundary and the second boundary.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Filip J. Pizlo, Oliver J. Hunt
  • Patent number: 10713153
    Abstract: A method and system generates extended patterns from base patterns with an automatic pattern generation engine. The method and system tests the extended patterns with an automatic pattern testing engine. The patterns correspond to configurations for implementing cloud-based applications. The patterns are extendable to make additional extended patterns. Extended patterns carry the characteristics of the patterns from which they were extended. Updating a base pattern with new security measures causes a cascade effect that updates all extended patterns that descend from the base pattern.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: Intuit Inc.
    Inventors: Sean McCluskey, Amit Kalamkar, Narender Kumar, Sriramu Singaram
  • Patent number: 10705838
    Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Vincent Onde
  • Patent number: 10698664
    Abstract: A method may include extracting information regarding a software project based on source code of the software project, where the information includes a description of the source code and computer-readable source code. The method may also include identifying at least two application programming interface (API) calls within the information, and extracting metadata regarding at least one of the APIs from the information. The method may additionally include, using the metadata, analyzing the computer-readable source code to determine a correlation between the two API calls. The method may also include, based on the correlation and using a first of the two API calls, generating computer source code that combines the first API call and an additional API call in an API mashup.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 30, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Mehdi Bahrami, Lei Liu, Wei-Peng Chen
  • Patent number: 10698678
    Abstract: A method for updating a firmware of a complex programmable logic device comprises: electrically connecting a general purpose input/output pin of a baseboard management controller with a hitless enable pin of a complex programmable logic device; electrically connecting a first integrated circuit bus of the baseboard management controller with a second integrated circuit bus of the complex programmable logic device; inputting and transmitting a update command to the baseboard management controller by a local operating system; enabling the hitless enable pin by the baseboard management controller according to the update command; cleaning a first firmware in the complex programmable logic device by the baseboard management controller according to the update command; and burning a second firmware into the complex programmable logic device by the baseboard management controller according to the update command.
    Type: Grant
    Filed: October 6, 2018
    Date of Patent: June 30, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Jian-Fei Liu, Hai-Tao Fang
  • Patent number: 10691430
    Abstract: An apparatus to facilitate instruction scheduling is disclosed. The apparatus includes one or more processors to receive a block of instructions, divide the block of instructions into a plurality of sub-blocks based on a register pressure bounded by a predetermined threshold and instructions in each of the plurality of sub-blocks for processing.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Wei Pan, Wei-Yu Chen, Guei-Yuan Lueh
  • Patent number: 10678518
    Abstract: A solution providing for the dynamic design, use, and modification of models using a declarative software application meta-model that provides for self-modification of a collection of the models is provided. The solution can enable continuous real-time testing, simulation, deployment, and modification of the collection of the models. A model in the collection of the models can represent an entity or a function and can be included in a set of related models. Additionally, a set of related models can include a plurality of sets of related models. The collection of the models can represent, for example, one or more software applications, processes, and/or the like.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 9, 2020
    Assignee: ENTERPRISEWEB LLC
    Inventors: Dave M. Duggal, William J. Malyk
  • Patent number: 10678864
    Abstract: An analysis model execution unit executing a part of an analysis model, an analysis model partial execution unit partially executing the analysis model based on intermediate data generated during execution of the analysis model, external storage storing the intermediate data and mapping information which is corresponding relationship between the intermediate data and the analysis model, and an analysis model general processing unit generating the mapping information by associating the intermediate data with the analysis model and reading the intermediate data associated with the analysis model from the external storage based on the mapping information are provided.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 9, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takaya Ide, Hiroshi Nasu, Yuki Naganuma, Toshio Nishida, Hideki Nakamura
  • Patent number: 10678523
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Srinivasan Ramani, Rohit Taneja