Abstract: Lighting systems with heat extracting light emitting elements are disclosed based on the light emitting surface also functioning as the heat cooling surface. Lighting systems which have only their light emitting surfaces exposed to ambient are disclosed. A thermally conductive mostly reflective light transmitting element provides light diffusion, interconnect, and forms a light recycling cavity providing very low profile and lightweight solid state light sources. These properties make these light sources very useful in applications such as aircraft, rescue, temporary illumination, and automotive where weight directly impacts cost and utility. The integration of drivers and other electrical functions onto the heat extracting light emitting elements is also disclosed.

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure. The raised source structure above is in contact with the first well and connected with the gate structure through a first semiconductor fin structure. The raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure. The second semiconductor fin structure includes at least a gap and a lightly doped portion.

Abstract: A solid-state light source with LEDs contained in a light recycling cavity emits both light and heat from heat extracting light emitting elements which form the light recycling cavity. Eliminating appended heat sinks makes these light sources ultra lightweight. The light sources can be attached and supported by suspended ceilings without affecting the seismic properties of the ceiling. The heat extracting light emitting elements are combined with a reflector to make directional light sources, which can be attached to ceilings with small magnets. Because the heat extracting light emitting elements transfer the heat from the light source to the illuminated area there is no requirement for disturbing or penetrating the ceiling barrier to a heat sink on the plenum side of the ceiling. This enables a contiguous acoustic ceiling. Further, the light sources are made from non flammable materials and therefore do not affect the fire rating of the ceiling.

Abstract: A pressure difference sensor includes a capsule, which has a ceramic capsule body. The capsule has a transducer seat in its interior, wherein there is arranged in the transducer seat a semiconductor pressure measuring transducer core, which has a measuring membrane body and at least one support body. The measuring membrane body is connected pressure-tightly with the at least one support body, which has a pressure inlet opening.

Abstract: A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two first soldering balls formed thereon. The chip includes a number of second bonding pads each corresponding to a first bonding pad. Each second bonding pad includes a second soldering ball. The two first soldering balls of a first bonding pad are electrically connected to the second soldering ball of a corresponding second bonding pad via two bonding wires.

Abstract: A high-resolution, Active Matrix (AM) programmed monolithic Light Emitting Diode (LED) micro-array is fabricated using flip-chip technology. The fabrication process includes fabrications of an LED micro-array and an AM panel, and combining the resulting LED micro-array and AM panel using the flip-chip technology. The LED micro-array is grown and fabricated on a sapphire substrate and the AM panel can be fabricated using PMOS process, NMOS process, or CMOS process. LED pixels in a same row share a common N-bus line that is connected to the ground of AM panel while p-electrodes of the LED pixels are electrically separated such that each p-electrode is independently connected to an output of drive circuits mounted on the AM panel. The LED micro-array is flip-chip bonded to the AM panel so that the AM panel controls the LED pixels individually and the LED pixels exhibit excellent emission uniformity.

Abstract: Described are embodiments to ensure that the equipment utilized to detect antigens is reliable and accurate. Accordingly, one embodiment of the invention includes a calibration assembly having nanoparticles, with known magnetic properties, spaced apart at known y-axis locations along the calibration assembly. In one embodiment, the calibration assembly may be used to calibrate a matched filter of the write and read circuitry. Because the calibration assembly comprises nanoparticles with known magnetic properties the read response of the read circuitry to a particular nanoparticle may be stored in the matched filter as an ideal signal for that nanoparticle. The ideal signal stored in the matched filter may then be utilized for reliably and accurately detecting antigens.

Abstract: A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.

Abstract: A semiconductor device includes a substrate, a metal film on a portion of the substrate, a first dielectric film having a first portion on the metal film and a second portion on the substrate, the second portion being integral with the first portion, a lower electrode on the first portion, a second dielectric film having a first portion on the lower electrode and a second portion on the first dielectric film, the second portion of the second dielectric film being integral with the first portion of said second dielectric film, an upper electrode on a portion of the second dielectric film, and a reinforcing film disposed on the second dielectric film and in contact with a side of the upper electrode.

Abstract: A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.

Abstract: A method of fabricating a semiconductor device includes providing a dummy gate insulation film formed on a substrate, the dummy gate insulation film including a first material and providing a spacer formed at least one side of the gate insulation film, the spacer including the first material, removing the first material included in the dummy gate insulation film by a first process, removing the dummy gate insulation film from which the first material has been removed by a second process different from the first process, and sequentially forming a gate insulation film and a gate electrode structure on the substrate.

Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.

Abstract: A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.

Abstract: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Abstract: An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed.

Abstract: A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Abstract: One or more embodiments relate to a method of making a semiconductor structure, comprising: forming a patterned metallic layer over a semiconductor substrate; forming a second layer over the patterned metallic layer; and etching the substrate.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type; a first electrode electrically connected to the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type selectively provided on the second semiconductor layer; a second electrode electrically connected to the second semiconductor layer and the third semiconductor layer; a third electrode and a floating electrode provided from an upper surface side of the third semiconductor layer through the third semiconductor layer and the second semiconductor layer to the first semiconductor layer via a first insulating film; a second insulating film provided between the second electrode and the third electrode, the second electrode and the floating electrode.

Abstract: A solid-state imaging device includes a photoelectric converting portion including a first semiconductor region capable of accumulating a signal charge, a second semiconductor region of the same conductivity type as the first semiconductor region, a gate electrode provided between the first and second semiconductor regions, and an insulating layer provided on the first semiconductor region, the second semiconductor region, and the gate electrode. The solid-state imaging device further includes a first light-shielding portion including a metal portion provided in an opening or a trench of the insulating layer between the first and second semiconductor regions, and a second light-shielding portion including a metal portion provided on the insulating layer on the second semiconductor region.

Abstract: A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.