Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract: A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.

Abstract: A mechanism is provided for base recognition of an integrated transistor and nanochannel. A target molecule is forced down to a carbon nanotube a single base at a time in the nanochannel by applying a gate voltage to a top electrode, and/or a narrow thickness of the nanochannel. The nanochannel exposes an exposed portion of the carbon nanotube at a bottom wall, and the top electrode is positioned over the exposed portion. The exposed portion of the carbon nanotube is smaller than the distance between bases to only accommodate the single base at a time. The target molecule is stretched by the narrow thickness and by applying a traverse voltage across a length direction of the nanochannel. The target molecule is frictionally restricted by the narrow thickness of the nanochannel to stretch is restrictedly translocates in the length direction. Current is measured to determine an identity of the single base.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.

Abstract: A mechanism is provided for base recognition of an integrated transistor and nanochannel. A target molecule is forced down to a carbon nanotube a single base at a time in the nanochannel by applying a gate voltage to a top electrode, and/or a narrow thickness of the nanochannel. The nanochannel exposes an exposed portion of the carbon nanotube at a bottom wall, and the top electrode is positioned over the exposed portion. The exposed portion of the carbon nanotube is smaller than the distance between bases to only accommodate the single base at a time. The target molecule is stretched by the narrow thickness and by applying a traverse voltage across a length direction of the nanochannel. The target molecule is frictionally restricted by the narrow thickness of the nanochannel to stretch is restrictedly translocates in the length direction. Current is measured to determine an identity of the single base.

Abstract: A method is provided for producing a radiation-emitting semiconductor chip, in which a first wavelength-converting layer is applied over the radiation exit face of a semiconductor body. The application method is selected from the following group: sedimentation, electrophoresis. In addition, a second wavelength-converting layer is applied over the radiation exit face of the semiconductor body. The second wavelength-converting layer is either produced in a separate method step and then applied or the application method is sedimentation, electrophoresis or printing. Furthermore, a radiation-emitting semiconductor chip and a radiation-emitting component are provided.

Abstract: A method for manufacturing a solar cell from a p-doped or n-doped silicon substrate having a first main surface used as an incident-light side and a second main surface used as a back side includes: depositing a thin layer onto the second main surface; depositing a dielectric, glass-forming paste onto the second main surface and drying it, in order to cover the thin layer; heating and/or sintering the paste on the second main surface at temperatures greater than app. 577° C., to produce an aluminum dopant layer in the second main surface; and removing the glass layer formed during the heating and/or sintering, as well as an aluminum-silicon eutectic layer formed during the heating and/or sintering, from the second main surface.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (?)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.

Abstract: Various embodiments include fin-shaped field effect transistor (finFET) structures that enhance work function and threshold voltage (Vt) control, along with methods of forming such structures. The finFET structures can include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). In some embodiments, the PFET has fins separated by a first distance and the NFET has fins separated by a second distance, where the first distance and the second distance are distinct from one another. In some embodiments, the PFET or the NFET include fins that are separated from one another by non-uniform distances. In some embodiments, the PFET or the NFET include adjacent fins that are separated by distinct distances at their source and drain regions.

Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

Abstract: In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P+ regions connected to a pixel selection line conductive layer are formed on top layer portions of upper ends of the island-shaped semiconductors so as to adjoin the N regions and the P regions. In the P+ regions, a first P+ region has a thickness less than a second P+ region, and the second P+ region has a thickness less than a third P+ region.

Abstract: Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region.

Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

Abstract: A method of making a non-volatile double-gate memory cell. A gate of the control transistor is formed with a relief on a substrate. A control gate of the memory transistor is formed with a layer of a semiconductor material covering relief. The method includes chemical mechanical polishing (CMP) so as to strip, above the relief another layer and part of the layer of a semiconductor material; stripping of the remaining other layer on both sides of the relief, etching of the layer of a semiconductor material so as to strip this material above the relief and to leave only a pattern on at least one sidewall of the relief.

Abstract: A semiconductor device and a manufacturing method thereof are provided. In one embodiment of the manufacturing method of the semiconductor device, a through electrode is formed on a semiconductor die, and a dielectric layer such as a photopolymer is coated on the through electrode to cover the through electrode. Under exposure is performed on the dielectric layer, thereby partially removing the dielectric layer by development. As a result, a top end of the through electrode is exposed to the outside or protrudes through the dielectric layer. The dielectric layer remaining on the top end of the through electrode may be removed by performing a plasma descum process, if needed.