Patents Examined by Changhyun Yi
  • Patent number: 12136657
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 12132113
    Abstract: A semiconductor device and a method for making a semiconductor device. The semiconductor device includes an active region on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers and including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Uk Jang, Young Dae Cho, Ki Hwan Kim, Su Jin Jung
  • Patent number: 12125852
    Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12125877
    Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 12119391
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12119347
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: October 15, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Patent number: 12119351
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 15, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Il Bae, Kang-Ill Seo
  • Patent number: 12113034
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chien-Hsuan Liu
  • Patent number: 12107131
    Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12107156
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 12100736
    Abstract: A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: September 24, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanhyeong Lee, Sangyong Kim, Jaejung Kim, Byounghoon Lee
  • Patent number: 12100738
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 12100746
    Abstract: A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Andrew M. Greene, Ruilong Xie, Maruf Amin Bhuiyan, Veeraraghavan S. Basker
  • Patent number: 12087633
    Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Kuo-Hsiu Hsu, Shih-Hao Lin, Shang-Rong Li, Ping-Wei Wang
  • Patent number: 12087722
    Abstract: An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 10, 2024
    Assignee: DEXERIALS CORPORATION
    Inventor: Yasushi Akutsu
  • Patent number: 12087839
    Abstract: In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant
  • Patent number: 12087817
    Abstract: A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 10, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 12080713
    Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsun Chiu, Ching-Wei Tsai, Yu-Xuan Huang, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 12080797
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: September 3, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dohyun Lee, Dongwoo Kim, Daeyong Kim, Rakhwan Kim
  • Patent number: 12080771
    Abstract: An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Georgios Vellianitis, Blandine Duriez