Patents Examined by Changhyun Yi
  • Patent number: 10468489
    Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Foley, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10439160
    Abstract: A display device includes: a substrate including a first pixel area (PA) and a second PA, the first PA being spaced apart from the second PA by a non-PA; a first pixel electrode (PE) overlapping the first PA; a second PE overlapping the second PA; a pixel-defining layer including a first opening overlapping the first PE and a second opening overlapping the second PE; a first intermediate layer (IL) on the first PE, the first IL including a first emission layer (EL); a second IL on the second PE, the second IL including a second EL spaced apart from the first EL; a first opposite electrode (OE) on the first IL; a second OE on the second IL, the second OE being spaced apart from the first OE; and a wiring layer (WL) overlapping the non-PA, the WL contacting respective portions of the first OE and the second OE.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jiyoung Choung, Arong Kim, Yeonhwa Lee
  • Patent number: 10439028
    Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: October 8, 2019
    Assignee: FLOSFIA, INC.
    Inventors: Toshimi Hitora, Masaya Oda, Akio Takatsuka
  • Patent number: 10439067
    Abstract: A display substrate is provided. The display substrate includes a gate interconnection disposed on an insulating substrate, an oxide semiconductor pattern disposed on the gate interconnection and including an oxide semiconductor, and a data interconnection disposed on the oxide semiconductor pattern to interconnect the gate interconnection. The oxide semiconductor pattern includes a first oxide semiconductor pattern having a first oxide and a first element and a second oxide semiconductor pattern having a second oxide.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Won Kim, Kap-Soo Yoon, Do-Hyun Kim, Hyun-Jung Lee
  • Patent number: 10439110
    Abstract: The invention provides a lighting system (100), configured to provide lighting system light (101), the lighting system comprising: —a light source (10) configured to provide light source light (11) with light intensity in the blue spectral region; —a first luminescent material (210) configured to convert at least part of the light source light (11) into first luminescent material light (211) with light intensity in the green spectral region and having a full width half maximum (FWHM) of at least 90 nm; —a second luminescent material (220) configured to convert (i) at least part of the light source light (11), or (ii) at least part of the light source light (11) and at least part of the first luminescent material light (211) into second luminescent material light (221) with light intensity in the spectral region of 610-680 nm; wherein the lighting system (100) is configured to provide at a first setting of the lighting system (100) lighting system light (101) comprising said light source light (11), said first
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 8, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Martinus Petrus Joseph Peeters, Rémy Cyrille Broersma, René Jan Hendriks
  • Patent number: 10431597
    Abstract: An RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; and a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 1, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Lucile Arnaud
  • Patent number: 10418385
    Abstract: An array substrate, a display panel, and a fabrication method of the array-substrate are provided. The array substrate comprises a first thin film transistor including a first metal oxide thin film transistor and disposed in a display region, a second thin film transistor including an amorphous silicon thin film transistor and disposed in a peripheral circuit region; and a third thin film transistor including a second metal oxide thin film transistor and disposed in the peripheral circuit region. A first insulating layer is disposed between a first metal oxide semiconductor layer and a first gate electrode, and a second insulating layer is disposed above the first gate electrode, a second gate electrode, and the first metal oxide semiconductor layer. The amorphous silicon semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode are disposed above the second insulating layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 17, 2019
    Assignees: Shanghai Tianma Micro-Electronics Co., Ltd., Tianma Micro-Electronics Co., Ltd.
    Inventors: Tianyi Wu, Jun Ma, Tianqing Hu
  • Patent number: 10407613
    Abstract: A semiconductor structure includes a quantum dot. A polymeric organic layer encapsulates the quantum dot to create a coated quantum dot, and at least one additional organic layer and/or inorganic insulator layer encapsulates the coated quantum dot, wherein forming the one or more layers of organic material that encapsulates the coated quantum dot comprises forming a plurality of layers of polymers using a layer-by-layer deposition process.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: September 10, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Weiwen Zhao, Juanita N. Kurtin
  • Patent number: 10408697
    Abstract: Techniques for improving implementation of a downhole tool string to be deployed in a borehole formed in a sub-surface formation. In some embodiments, a design device determines a model that describes expected relationship between properties of the downhole tool string, the borehole, the sub-surface formation, and mud cake expected to be formed in the borehole; determines calibration locations along the borehole based on properties of the borehole; determines candidate spacer configurations based on contact force expected to occur at contact points between the downhole tool string and the mud cake when deployed with each of the candidate spacer configuration via the model; and determines a final spacer configuration to be used to attach one or more spacers along the downhole tool string based on expected head tension to move the downhole tool string when deployed in the borehole with each of the candidate spacer configurations via the model.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 10, 2019
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Kai Hsu, Scott C. Cook, Daniel Schulz, Gregory Au, Samuel P. Subbarao, Abhishek Agarwal, Ashers Partouche
  • Patent number: 10411135
    Abstract: Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 10, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Joanne Huang, Jamil Kawa
  • Patent number: 10403693
    Abstract: A display apparatus and a method for producing the same are disclosed. The display apparatus includes a display panel, a first antistatic pattern, and an electronic component. The electronic component has a second antistatic pattern. The first antistatic pattern and the electronic component are provided at a side of the display panel away from the light-emitting side thereof in an inlaid manner.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 3, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OTPOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hao Wu, Xiaoping Zhang, Ying Liu, Lingguo Wang, Jianguo Zhu, Hongjun Yu, Xin Wang, Na An, Baolei Guo
  • Patent number: 10398233
    Abstract: A furniture system includes a chair having a seat, a backrest coupled to the seat, and a base supporting the backrest and the seat. The furniture system also includes a plurality of sensors and a processor. Each sensor is operable to detect a physical force imparted by a user on the chair, and generate an output signal indicative of the physical force. The processor is coupled to the plurality of sensors, and is operable to receive the output signals generated by the plurality of sensors, and determine, based on at least one of the output signals, a current posture of the user sitting in the chair.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 3, 2019
    Assignee: HERMAN MILLER, INC.
    Inventors: Christopher Hoyt, Daniel Rucker, Joseph Doran, Brian Alexander, Adam Daley-Fell
  • Patent number: 10396201
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • Patent number: 10396284
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shu-Jen Han
  • Patent number: 10396314
    Abstract: There is provided a manufacturing method for an organic electroluminescent panel that includes an organic electroluminescent element for each sub-pixel. The manufacturing method includes an application step of recoating a first organic material layer and a second organic material layer, which include principal components common to each other, to manufacture the organic electroluminescent element. At the application step, after the first organic material layer is applied, an insolubilization process is performed for the first organic material layer to provide a change to a structure of molecules included in the first organic material layer, and the second organic material layer is applied to the first organic material layer after the insolubilization process is performed.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 27, 2019
    Assignee: JOLED INC.
    Inventor: Masakazu Takata
  • Patent number: 10397331
    Abstract: Systems and methods are presented for a mobile device comprising an industrial internet application container comprising a database service for syncing data related to one or more industrial assets between a database of the mobile device and a data domain and syncing data between the data domain and the database of the mobile device.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 27, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Michael Hart, Milton Waid, Andy Johns, Jeremy Osterhoudt
  • Patent number: 10396251
    Abstract: Various embodiments may relate to A light-emitting diode, including an LED chip having at least one emitter surface for emitting primary light, and a plurality of luminescent regions, which are connected optically downstream from the at least one emitter surface. At least one harder one of the luminescent regions is embedded in another, softer one of the luminescent regions.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: August 27, 2019
    Assignee: OSRAM GMBH
    Inventors: Andreas Biebersdorf, Florian Boesl, Krister Bergenek, Ralph Wirth
  • Patent number: 10386825
    Abstract: An I/O-abstracted configuration is defined for a field device that has not yet been assigned or allocated to communicate via a particular I/O device, and the field device (and optionally portions of the process control loop of which the field device is a part) is commissioned based on contents of its I/O-abstracted configuration. The field device's I/O-abstracted configuration is stored in an instance of a device placeholder object, which may be common to multiple types of devices and multiple types of I/O. A property of the device placeholder object may be exposed based on the value entered for another property, and the device placeholder object may store abstracted values as well as explicit or discrete values that are descriptive of the field device and its behavior. Upon I/O-assignment or allocation, values held in the device's I/O-abstracted configuration may be transferred to or otherwise synchronized with the device's as-built configuration.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 20, 2019
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Larry O. Jundt, Cristopher Ian S. Uy, Deborah R. Colclazier, Sergio Diaz, Gary K. Law, Julian K. Naidoo, Daniel R. Strinden, Kent A. Burr, Neil J. Peterson
  • Patent number: 10388786
    Abstract: A ferroelectric memory device is disclosed. The ferroelectric memory device includes a substrate, an indium-gallium-zinc oxide layer disposed on the substrate, a ferroelectric material layer disposed on the indium-gallium-zinc oxide layer, a gate electrode layer disposed on the ferroelectric material layer, and a source electrode layer and a drain electrode layer that are disposed the ends of the gate electrode. The indium-gallium-zinc oxide layer is recessed to form a trench at the ends of the gate electrode. The trench is filled with a conductive material to form the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Sanghun Lee, Yong Soo Choi
  • Patent number: 10381454
    Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 13, 2019
    Assignee: PATTERSON + SHERIDAN LLP
    Inventors: Xuena Zhang, Dong-Kil Yim, Wenqing Dai, Harvey You, Tae Kyung Won, Hsiao-Lin Yang, Wan-Yu Lin, Yun-chu Tsai