Patents Examined by Changhyun Yi
  • Patent number: 11515424
    Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
  • Patent number: 11515394
    Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 29, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Etienne Eustache, Bassem Salem, Jean-Michel Hartmann, Franck Bassani, Mohamed-Aymen Mahjoub
  • Patent number: 11515421
    Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junggun You, Joohee Jung, Jaehyeoung Ma, Namhyun Lee
  • Patent number: 11515297
    Abstract: Micro light-emitting diode displays having colloidal or graded index quantum dot films and methods of fabricating micro light-emitting diode displays having colloidal or graded index quantum dot films are described. In an example, a micro light emitting diode pixel structure includes a plurality of micro light emitting diode devices in a dielectric layer. A transparent conducting oxide layer is above the dielectric layer. A material layer is on the transparent conducting oxide layer, the material layer having a portion with a hydrophilic surface and a portion with a hydrophobic surface, the hydrophilic surface over one of the plurality of micro light emitting diode devices. A color conversion film is on the hydrophilic surface of the material layer and over the one of the plurality of micro light emitting diode devices.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Andrew William Keates
  • Patent number: 11515349
    Abstract: A semiconductor unit includes: a semiconductor substrate; a first groove provided in the semiconductor substrate, having a first width W1 and extending in a first direction; and a second groove provided in the semiconductor substrate in communication with the first groove, having a second width W2 different from the first width, and extending in a second direction that intersects the first direction, in which one of the first groove and the second groove is used for alignment.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 29, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tokihisa Kaneguchi
  • Patent number: 11515393
    Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer comprises a first part and a second part below the first part. The second part comprises a first portion disposed adjacent a first semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the first portion having a first radius of curvature, a second portion below the first portion and in contact with a second semiconductor layer of the plurality of semiconductor layers, and a third portion below the second portion and in contact with a third semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the third portion having a second radius of curvature greater than the first radius of curvature.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shu-Wen Shen
  • Patent number: 11515325
    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11508828
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
  • Patent number: 11502170
    Abstract: Some embodiments of the present disclosure provide a semiconductor device, including a substrate, a channel layer, a barrier layer, a p-type doped III-V layer, a source, a drain and a doped semiconductor layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The p-type doped III-V layer is disposed on the barrier layer. A gate is disposed on the p-type doped III-V layer. The source and the drain are arranged on two opposite sides of the gate. The doped semiconductor layer is provided with a first side close to the gate and a second side away from the gate. The drain covers the first side of the doped semiconductor layer.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 15, 2022
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: King Yuen Wong, Ronghui Denys Hao
  • Patent number: 11502274
    Abstract: A display substrate includes a base substrate, a display structure layer arranged on the base substrate, a first encapsulation layer, a first protection layer, a color filter layer, a second protection layer and a second encapsulation layer sequentially superposed on the display structure layer. Also provided is a preparation method of a display substrate and a display apparatus.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 15, 2022
    Assignees: Chongqing BOE Display Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Jie Li, Huaisen Ren, Wei Xia
  • Patent number: 11502201
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Shih-Chuan Chiu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11502147
    Abstract: A display device a includes: a transistor disposed on a first substrate; an insulating layer disposed on the transistor; a first electrode disposed on the insulating layer; a partition disposed on the first electrode and the insulating layer, an opening is defined through the partition; a light-emitting element layer disposed in the opening; and a second electrode disposed on the light-emitting element layer and the partition. The insulating layer includes a first region and a third region having different heights from each other and a second region having an inclined surface connecting the first region and the third region, the first region has a lower height than the third region, and the first electrode overlaps the first region in a direction perpendicular to the first substrate.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Min Chul Shin
  • Patent number: 11495541
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongsoon Lim, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Hongsoo Jeon, Yonghyuk Choi
  • Patent number: 11495673
    Abstract: A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 11488969
    Abstract: A semiconductor structure includes an array of two-port (TP) SRAM cells, each of which includes a write port and a read port. The write port includes two write pass gate (W_PG) transistors, two write pull-down (W_PD) transistors, and two write pull-up (W_PU) transistors. The array of TP SRAM cells includes first and second TP SRAM cells whose write ports abuts each other. Two W_PG transistors of the first and second TP SRAM cells share a common gate electrode. Source/drain electrodes of two W_PD transistors of the first and second TP SRAM cells share a common contact. The first TP SRAM cell includes a Vss conductor connected to the common contact. The second TP SRAM cell includes a write word line (W_WL) landing pad connected to the common gate electrode. The Vss conductor and the W_WL landing pad are located at a first metal layer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11489045
    Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 11489006
    Abstract: Provided are a display panel, a preparation method thereof and a display device. The display panel includes a substrate; a driving circuit layer, where the driving circuit layer is disposed on a side of the substrate, and includes a plurality of driving circuits; and an LED element layer, where the LED element layer is disposed on a side of the driving circuit layer facing away from the substrate, and includes a plurality of micro-LED elements, where each of the plurality of micro-LED elements is electrically connected to a respective one of the plurality of driving circuits through a via hole.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 1, 2022
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventors: Wenjun Dai, Liang Xing, Tianyi Wu, Yuan Ding
  • Patent number: 11485908
    Abstract: A quantum dot light-emitting diode and a method for fabricating the same. The quantum dot light-emitting diode, includes: an anode, a cathode, and a quantum dot light-emitting layer arranged between the anode and the cathode. A composite electron transport layer is arranged between the cathode and the quantum dot light-emitting layer, and the composite electron transport layer contains an electron transport material and an ultraviolet absorbing material.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 1, 2022
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Zhurong Liang, Weiran Cao, Lei Qian
  • Patent number: 11482596
    Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.
    Type: Grant
    Filed: March 21, 2021
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinbum Kim, Seokhoon Kim, Kwanheum Lee, Choeun Lee, Sujin Jung
  • Patent number: 11482604
    Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a substrate; forming a doped source/drain layer on a surface of the substrate; forming a channel pillar on the doped source/drain layer; forming a work function layer on side and top surfaces of the channel pillar; and forming a first isolation layer on the doped source/drain layer. The first isolation layer is on a portion of a sidewall surface of the work function layer. The method also includes forming a gate electrode layer on a surface of the work function layer and a surface of the first isolation layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou