Patents Examined by Changhyun Yi
  • Patent number: 11073807
    Abstract: Method and apparatus for controlling power conditioners in a distributed resource island. In one embodiment, the method comprises comparing, at a power conditioner operating in a de-energized state, an input of the power conditioner to an input threshold, wherein the power conditioner is coupled to an islanded grid; operating the power conditioner, when the input exceeds the input threshold, in a soft-grid mode to generate a touch-safe AC voltage that is coupled to the islanded grid; and activating the power conditioner, based on an impedance of the islanded grid and load demand for the power conditioner, to operate proximate its nominal output voltage.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 27, 2021
    Assignee: Enphase Energy, Inc.
    Inventors: Donald Richard Zimmanck, Christopher N. Rowe, John Scott Berdner
  • Patent number: 11075364
    Abstract: A display device comprises a display panel; a light control layer disposed on one side of the display panel through which light is transmitted, the light control layer including a plurality of light absorption patterns spaced apart from each other; and a plurality of reflection patterns disposed under the plurality of light absorption patterns and reflecting light travelling toward to the plurality of light absorption patterns.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 27, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dong-Yul Kim, Nack-Bong Choi
  • Patent number: 11069781
    Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 20, 2021
    Assignee: FLOSFIA INC.
    Inventors: Toshimi Hitora, Masaya Oda, Akio Takatsuka
  • Patent number: 11069827
    Abstract: A semiconductor device includes a substrate having a mounting surface, a plurality of internal terminals disposed on the mounting surface, a light-receiving element mounted on the mounting surface, a light-emitting element mounted on the mounting surface, a first bonding wire and a light-transmitting element. The light-receiving element has a light-receiving region that detects light and a plurality of element pad portions. At least one of the plurality of element pad portions is electrically connected to the light-receiving region. The light-emitting element is spaced apart from the light-receiving element along a first direction perpendicular to a thickness direction of the substrate. The first bonding wire connects one of the plurality of element pad portions of the light-receiving element to one of the plurality of internal terminals. The first bonding wire is located on a side of the light-receiving element opposite the light-emitting element along the first direction.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: July 20, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Hideyuki Utsumi
  • Patent number: 11069681
    Abstract: An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keomyoung Shin, Pankwi Park, Seunghun Lee
  • Patent number: 11056590
    Abstract: In a general aspect, an integrated circuit (IC) can include a low-voltage region including a low-side driver circuit configured to control a low-side switch of a power converter. The IC can also include a high-voltage region including a floating region of a first conductivity and a high-voltage sensing device disposed in the floating region. The high-voltage sensing device can include a junction-field effect transistor (JFET), and a voltage divider. The voltage divider can include a first terminal coupled to a drain of the JFET, a second terminal coupled to a gate of the JFET, and a sense terminal, the voltage divider being configured to a provide, on the sense terminal. The IC can further include a high-side driver circuit coupled with the sense terminal. The high-side driver circuit can be configured to control a high-side switch of the power converter based on the voltage on the sense terminal.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: July 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold, Richard Taylor
  • Patent number: 11050017
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 29, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
  • Patent number: 11049853
    Abstract: An electronic device includes a silicon-on-insulator (SOI) structure, and an electrostatic discharge (ESD) protection device, with an isolation layer having a thickness and extending in a trench from a first implanted region. The ESD protection device includes a conductive field plate that extends over a portion of the first implanted region and past the first implanted region and over a portion of the isolation layer by an overlap distance that is 3.5 to 5.0 times the thickness of the isolation layer. In one example, the ESD protection device has a finger or racetrack shape, and the first implanted region and a second implanted region extend around first and second turn portions of the finger shape.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11037888
    Abstract: The present invention relates to a nitride-based electronic device and a method for manufacturing same, the nitride-based electronic device comprising a substrate, a metal electrode and a plurality of protection layers, wherein, among the protection layers, at least two protection layers covering one portion of the electrode so that one portion of the upper part of the electrode is exposed are configured so that the upper protection layer covers the end part of the lower protection layer so as to prevent the end part of the lower protection layer from being exposed.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 15, 2021
    Assignee: WAVICE INC.
    Inventors: Sang Min Lee, Hwang Sub Koo, Hyun Je Kim, Hee seok Jung
  • Patent number: 11037845
    Abstract: A semiconductor device includes: a semiconductor chip; a case storing the semiconductor chip; a wire bonded to the semiconductor chip; a cover fixed inside the case and including a concave portion disposed above the semiconductor chip and the wire; and a sealing resin potted inside the case and sealing the semiconductor chip, the wire and the cover, wherein the sealing resin is not filled in the concave portion so that a cavity is provided.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 15, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Masumoto
  • Patent number: 11031469
    Abstract: A semiconductor device, a manufacturing method thereof, and an electronic device including the same are provided. According to an embodiment, the semiconductor device may include a substrate; a first source/drain region, a channel region and a second source/drain region stacked on the substrate in sequence and contiguous to each other, and a gate stack formed surrounding a periphery of the channel region; wherein spacers are respectively provided between the gate stack and the first source/drain region and between the gate stack and the second source/drain region in a form of surrounding the periphery of the channel region.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 8, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11031502
    Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Uk Jang, Young Dae Cho, Ki Hwan Kim, Su Jin Jung
  • Patent number: 11023805
    Abstract: A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Atsuya Okazaki, Junka Okazawa, Takayuki Osogami
  • Patent number: 11024741
    Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungmin Song, Bongseok Suh, Junggil Yang, Soojin Jeong
  • Patent number: 11018324
    Abstract: A stretchable display device includes a structure that can minimize damage to a polarizing layer when the stretchable display device is stretched and reduce visibility of external light being reflected to a user by using a polarizing plate having a stretchable characteristic, and the thickness of the stretchable display can be reduced because components disposed under the upper substrate and the polarizing layer are configured to include the same material as the polarizing layer that can be easily stretched in a plurality of directions by alternately disposing stretchable polarizing layers in different directions.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 25, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kihan Kim, Hyokang Lee, Hohyun Keum
  • Patent number: 11016477
    Abstract: Devices, methods, and systems for distributed rule based automated fault detection are described herein. One system includes a data extractor engine configured to: extract configuration data relating to an environment based on a number of defined rules, and receive monitored data relating to the environment, an AFD engine configured to evaluate the monitored data in view of the configuration data to determine a state of the environment, and a fault generation engine to determine whether the state of the environment is outside a range defined by the number of defined rules.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 25, 2021
    Assignee: Honeywell International Inc.
    Inventors: Jitendra Singh, Arvind R. Shetty, Rajesh V. Poojary, Manu Taranath, Greg Bernhardt
  • Patent number: 11018264
    Abstract: Described herein are three-dimensional nanoribbon-based logic ICs that include one of more of 1) individual gate control in a vertical stack of nanoribbons, 2) inter-ribbon interconnects in a vertical stack of nanoribbons, and 3) both P- and N-type nanoribbons in a vertical stack of nanoribbons. Using one or more of these features may help realize unique monolithic 3D logic architectures that were not possible with conventional logic circuits and may allow realizing logic devices with favorable metrics in terms of power and performance while preserving the substrate area and cost.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Tahir Ghani, Rajesh Kumar
  • Patent number: 11017350
    Abstract: Interposer assemblies may be inserted between a traditional shelf and traditional supports for the shelf. Each of the interposer assemblies may be configured to generate signals corresponding to changes in loading on the traditional shelf, and information regarding the changes may be determined to identify items placed onto or removed from the traditional shelf, and locations at which the items were placed or from which the items were removed. The interposer assemblies may include one or more load cells, such as strain-gage load cells, and analog signals generated by the load cells may be processed to determine a mass of an item placed on the shelf or removed therefrom. The item, and a location corresponding to the item, may be determined based on the mass and according to standard equilibrium procedures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 25, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeremy Samuel De Bonet, Nicholas Charles McMahon, Jacob Alex Siegel
  • Patent number: 11011510
    Abstract: An electronic device includes an ESD protection device with implanted regions that extend around a finger shape with a straight portion and elongated turn portions, and contacts that extend only in the straight portion, where the turn portions include elongated lightly doped implanted regions to mitigate turn on of a curvature PNP transistor for uniform device breakdown performance. Adjacent finger structures are spaced apart from one another to mitigate thermal transfer between device fingers.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 11009862
    Abstract: A system for monitoring manufacturing includes one or more sensors and a controller in communication with the one or more sensors. The controller may include one or more processors that determine a quality metric represented by machine data collected from one or more machine data sensors and identify a correlation value between the machine data and environmental data collected from one or more environmental data sensors. The controller may further include determine if the correlation value exceeds a predetermined threshold value, and if the correlation value exceeds the predetermined threshold value, report at least one of the correlation value and the quality metric.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 18, 2021
    Assignee: Sight Machine, Inc.
    Inventors: Nathan Oostendorp, Kurtis Alan Demaagd, Ryan Smith