Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A display device includes a display layer having a plurality of light-emitting diodes and an encapsulation layer covering a light-emitting side of the display layer. The encapsulation layer includes a plurality of first polymer projections on display layer, the plurality of first polymer projections having spaces therebetween, and a first dielectric layer conformally covering the plurality of first polymer projections and any exposed underlying surface in the spaces between the first polymer projections, the dielectric layer forming side walls along sides of the first polymer projections and defining wells in spaces between the side walls.

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: A method of manufacturing a polycrystalline silicon layer for a display device includes the steps of forming an amorphous silicon layer on a substrate, cleaning the amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

Abstract: A display device includes a substrate includes a first emitter and a second emitter thereon. The first emitter includes a first lower active quantum well (QW) region that has a first emission spectrum spanning a first spectral range. The second emitter includes (i) an upper active QW region that has a second emission spectrum spanning a second spectral range that is distinct from the first spectral range, (ii) a second lower active QW region having the first emission spectrum and being located between the upper active QW region and the substrate, and (iii) a barrier layer between the second lower active QW region and the upper active QW region for suppressing emission of the second lower active QW region.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: The semiconductor device may include an active pattern provided on a substrate and a source/drain pattern on the active pattern. The source/drain pattern may include a bottom surface in contact with a top surface of the active pattern. The semiconductor device may further include a channel pattern connected to the source/drain pattern, a gate electrode extended to cross the channel pattern, and a fence insulating layer extended from a side surface of the active pattern to a lower side surface of the source/drain pattern. A pair of middle insulating patterns may be at both sides of the bottom surface of the source/drain pattern and between the active pattern and the source/drain pattern in contact with an inner side surface of the fence insulating layer.

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.