Abstract: An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.

Abstract: In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

Abstract: According to some aspects, an imaging device is provided comprising a photoelectric conversion layer configured to receive light and to produce an electric charge in response to the received light, including a first filter region corresponding to a first pixel of the imaging device, the first filter region having a first thickness and a plurality of through holes formed therein, wherein the first filter region transmits light incident on the first filter region with a first peak transmission wavelength, and a second filter region corresponding to a second pixel of the imaging device, the second filter region having a second thickness greater than the first thickness and having a plurality of through holes formed therein, wherein the second filter region transmits light incident on the second filter region with a second peak transmission wavelength that is greater than the first peak transmission wavelength.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.

Abstract: Embodiments of the disclosure are related to a display device, in a structure where an optical sensor is disposed on an opposite side of a side displaying an image and overlapping an active area of a display panel, as increasing a transmittance by implementing an area overlapping to the optical sensor as a low resolution area, a sensing function by the optical sensor located in the active area could be implemented. Furthermore, by implementing a number of a gate electrode or a width of a channel region or the like of a driving transistor disposed in the low resolution area to be different from those of a driving transistor disposed in a high resolution area, compensating a luminance of the low resolution area and preventing a deviation of a luminance between the low resolution area and the high resolution area can be achieved.

Abstract: MEMS-based sensors can experience undesirable signal frequencies caused by vibrations, shocks, and accelerations, among other phenomena. A microisolation system can isolate individual MEMS-based sensors from undesirable signal frequencies and shocks. An embodiment of a system for microisolation of a MEMS-based sensor can include an isolation platform connected to one or more folded springs. Another embodiment of a system for microisolation can include an isolation platform and/or a frame connected to a mesh damping mechanism. In at least one embodiment, a mesh damping mechanism can be a microfibrous metal mesh damper. In one or more embodiments, a system for microisolation can include an isolation platform connected to one or more L-shaped springs, and a thickness of the one or more L-shaped springs can be less than a thickness of the isolation platform.

Abstract: A semiconductor device includes a semiconductive substrate, a semiconductive fin, an isolation structure, a source/drain epitaxial structure, a first cap layer, and a second cap layer. The semiconductive fin protrudes from the semiconductive substrate. The isolation structure is over the semiconductive substrate and laterally surrounds the semiconductive fin. The source/drain epitaxial structure is over the semiconductive fin. The source/drain epitaxial structure has a rounded corner extending laterally and a top above the rounded corner. The first cap layer extends from the rounded corner of the source/drain epitaxial structure to the top of the source/drain epitaxial structure. The second cap layer covers the rounded corner and a bottom of the source/drain epitaxial structure. The first and second cap layers are made of different materials.

Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

Abstract: A method for processing a forksheet device includes providing a substrate and forming a trench in the substrate, extending along a first direction, in the substrate. The formation of the trench includes forming a grating structure on the substrate that includes a pair of maskings, arranged at a distance from each other, and etching the trench into the substrate in a region between the pair of maskings. The method also includes filling the trench with a filling material and partially recessing the substrate to form a fin structure. This fin structure includes the filled trench, a first section of the substrate at a first side of the filled trench and a second section of the substrate at a second side of the filled trench, and forming a gate structure on and around the fin structure. The method additionally includes forming a gate structure on and around the fin structure.

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.

Abstract: A stretchable display device comprises a lower substrate, a plurality of island substrates disposed on the lower substrate and spaced apart from each other, a plurality of display elements disposed on the plurality of island substrates, a plurality of connecting lines disposed between each of the plurality of island substrates, an upper substrate disposed on the lower substrate, the plurality of display elements and the plurality of connecting lines, and a polarizing layer disposed on the upper substrate and including a phase delay layer on the upper substrate and a linear polarizing plate on the phase delay layer, wherein the phase delay layer includes a first base polymer, wherein the linear polarizing plate includes a second base polymer, and wherein the first and second base polymers include a same material as the upper substrate.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: A semiconductor device includes a semiconductor layer of first-conductivity-type that has a main surface and that includes an active region set at the main surface, a current detection region set at the main surface away from the active region, and a boundary region set in a region between the active region and the current detection region at the main surface, a first body region of second-conductivity-type formed in a surface layer portion of the main surface at the active region, a first trench gate structure formed in the main surface at the active region, a second body region of second-conductivity-type formed in the surface layer portion of the main surface at the current detection region, a second trench gate structure formed in the main surface at the current detection region, a well region of second-conductivity-type formed in the surface layer portion of the main surface at the boundary region, and a dummy trench gate structure formed in an electrically floating state in the main surface at the bound

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.