Patents Examined by Charles Miller
  • Patent number: 5381252
    Abstract: A projection liquid crystal display (LCD) system includes a liquid crystal display panel including a first plurality of horizontally aligned transparent conductive scanning electrodes and a second plurality of vertically aligned transparent conductive signal electrodes disposed on opposed surfaces of the panel. Light directed onto the display panel's aft surface is transmitted through the panel as each horizontal linear array of electrodes is turned "ON", with the horizontal linear arrays sequentially turned on for vertically scanning the display panel in a stepwise manner. LCD backlighting is provided by a cathode ray tube (CRT) having a phosphorbearing faceplate which emits light when an electron beam is incident thereon. The CRT includes two electron beams which are directed onto the faceplate's inner phosphor layer and are deflected in opposed directions along a common horizontal scan line, where each horizontal scan line on the CRT's faceplate is traced in sequence by the two beams.
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: January 10, 1995
    Assignee: Chunghawa Picture Tubes, Ltd.
    Inventor: Hsing-Yao Chen
  • Patent number: 5373378
    Abstract: Pixel electrodes in the periphery of a thin film transistor array (peripheral part of the display screen) of an active matrix type liquid crystal display device are directly electrically shortcircuited with signal lines, whereby an alternating current signal is always applied to the pixel electrodes without being passed through a thin film transistor as a switching element. Thereby the liquid crystal arranged on the peripheral part of the display screen is driven in a static state resulting in a high stability against the display characteristics.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: December 13, 1994
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Yoneharu Takubo, Ikunori Kobayashi, Tetsu Ogawa
  • Patent number: 5373379
    Abstract: Disclosed is a wiring for an electronic circuit, comprising a substrate, a first conductor layer formed on said substrate, an insulating layer formed on said insulating layer, and a second conductor layer formed on said insulating layer such that said second conductor layer overlaps with at least a part of said first conductor layer, wherein an inner portion of at least one of the overlapping portions of said first conductor layer and said second conductor layer is removed at least partially to cause the peripheral portion to remain unremoved at least partially, thereby decreasing the area of the overlapping portion.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: December 13, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Nakai