Patents Examined by Charles N Ausar-El
  • Patent number: 10991660
    Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 27, 2021
    Assignee: ALPHA ANC OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Long-Ching Wang, Zhen Du, Bo Chen, Jun Lu, Yueh-Se Ho
  • Patent number: 10937994
    Abstract: An organic electroluminescence display device includes, from a visible side, at least: a circular polarization plate; and an organic electroluminescence display element having a pair of electrodes and an organic light emitting layer sandwiched therebetween. A high refractive index layer has a refractive index of greater than 1.7 and less than 2.1 is disposed between the plate and one of the electrodes on the visible side, the plate has a polarizer, a ?/2 plate, and a ?/4 plate in this order from the visible side, a retardation RthA (550) of the ?/2 plate in a thickness direction at a wavelength of 550 nm is within a range of greater than ?120 nm and less than ?40 nm, and a retardation RthB (550) of the ?/4 plate in a thickness direction at a wavelength of 550 nm is within a range of greater than ?60 nm and less than 20 nm.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 2, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Shinpei Yoshida
  • Patent number: 10921651
    Abstract: A display panel, a display device, and a method for manufacturing a display panel are provided. The display panel includes an array substrate, a color film substrate, and support pillars located between the array substrate and the color filter substrate. The array substrate includes sub-pixels, multiple gate lines, multiple data lines and a common electrode line. The common electrode line includes a first wire portion extending in a first direction and located between two adjacent sub-pixels. The data lines include multiple support sections each located at an intersection of the data line with the first wire portion. An orthographic projection of each of the support sections on the base substrate is a support region. A side of the support pillar close to the array substrate is located in the support region.
    Type: Grant
    Filed: November 11, 2018
    Date of Patent: February 16, 2021
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Lei Wang, Mingwei Zhang, Xiangjian Kong, Jin'e Liu, Feng Qin
  • Patent number: 10923471
    Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty
  • Patent number: 10923570
    Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa
  • Patent number: 10903441
    Abstract: Single-layer LEDs were developed using a composite thin film of organometal halide perovskite (Pero) and poly (ethylene oxide) (PEO). Single-layer Pero LEDs have a device structure that resembles “bottom electrode (ITO)/Pero-PEO/top electrode (In/Ga or Au)”. Green emission LEDs with methylammonium lead bromide (bromide-Pero) and PEO composite thin films exhibit a low turn-on voltage of about 2.8-3.1 V (defined at 1 cd m?2 luminance), a maximum luminance of 4064 cd m?2 and a moderate maximum current efficiency of about 0.24-0.74 cd A?1. Blue and red emission LEDs have also been fabricated using Cl/Br or Br/I alloyed Pero-PEO composite thin films.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 26, 2021
    Assignee: The Florida State University Research Foundation, Inc.
    Inventors: Zhibin Yu, Junqiang Li, Sri Ganesh Rohit Bade
  • Patent number: 10903215
    Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10896885
    Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 19, 2021
    Assignees: Polar Semiconductor, LLC, Sanken Electric Co., Ltd.
    Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
  • Patent number: 10892298
    Abstract: A light emitting diode display device is provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tan Sakong, Yong Il Kim, Jong Uk Seo, Ji Hye Yeon
  • Patent number: 10847678
    Abstract: An embodiment comprises: a light emitting structure comprising a substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, and an active layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a light transmissive conduction layer arranged on the second conductive type semiconductor layer. The light transmissive conduction layer comprises: a first conductive oxide layer arranged on the first conductive type semiconductor layer and comprising at least one first metal element and oxygen; and a second conductive oxide layer arranged on the first conductive oxide layer and comprising a compound consisting of the same metal element as the at least one first metal element, a second metal element, and oxygen.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 24, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventor: Se Yeon Jung
  • Patent number: 10811325
    Abstract: Implementations of the present disclosure generally relate to methods for processing substrates, and more particularly, to methods for predicting, quantifying and correcting process drift. In one implementation, the method includes performing a design of experiments (DOE) in a process chamber to obtain sensor readings and film properties at multiple locations on a substrate for every adjustable process control change associated with the process chamber, building a regression model for each location on the substrate using the sensor readings and film properties obtained from the DOE, tracking changes in sensor readings during production, identifying drifting in sensor readings that can lead to a change in film properties using the regression model, and adjusting one or more process controls to correct the drifting in sensor readings to minimize the change in film properties.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 20, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Abdul Aziz Khaja
  • Patent number: 10811523
    Abstract: A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 20, 2020
    Assignee: ABLIC INC.
    Inventors: Mitsuhiro Yoshimura, Masahiro Hatakenaka
  • Patent number: 10741651
    Abstract: A terminal structure of an insulated gate bipolar transistor (IGBT) device includes a main junction, a cutoff ring, and a plurality of terminal rings disposed between the main junction and the cutoff ring, and a resistive element having a first terminal electrically connected to the main junction, a second terminal electrically connected to the cutoff ring, and a plurality of intermediate terminals electrically connected to the terminal rings, respectively. The resistive element is configured to uniformly distribute the lateral voltage between the main junction and the cutoff ring to the terminal rings to ensure that the peak electric field is uniformly distributed across the terminal structure, thereby reducing the terminal structure area and package cost of the IGBT device, while improving the device reliability.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 11, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Jian Liu
  • Patent number: 10741682
    Abstract: High-electron-mobility transistor (HEMT) devices are described in this patent application. In some implementations, the HEMT devices can include a back barrier hole injection structure. In some implementations, the HEMT devices include a conductive striped portion electrically coupled to a drain contact.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Woochul Jeon, Ali Salih, Llewellyn Vaughan-Edmunds
  • Patent number: 10740531
    Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Patent number: 10727320
    Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10707082
    Abstract: Atomic layer deposition (ALD) processes for forming thin films comprising InN are provided. The thin films may find use, for example, in light-emitting diodes.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 7, 2020
    Assignee: ASM International N.V.
    Inventors: Suvi Haukka, Viljami J. Pore, Antti Niskanen
  • Patent number: 10700037
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Patent number: 10685905
    Abstract: A multi-layer cooling structure comprising a first substrate layer comprising an array of cooling channels, a second substrate layer comprising a nozzle structure that includes one or more nozzles, an outlet, and an outlet manifold, a third substrate layer comprising an inlet manifold and an inlet, and one or more TSVs disposed through the first substrate layer, second substrate layer, and third substrate layer. At least one of the one or more TSVs is metallized. The first substrate layer and the second substrate layer are directly bonded, and the second substrate layer and the third substrate layer are directly bonded.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 16, 2020
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Feng Zhou, Ki Wook Jung, Ercan M. Dede
  • Patent number: 10672876
    Abstract: A field-effect transistor includes a source electrode, a drain electrode, a semiconductor structure including a channel provided between the source electrode and the drain electrode in a first direction. Gate main portions have a first gate main portion length in the first direction and a second gate main portion length in a second direction. Connection portions are alternatively connected to the gate main portions respectively in the second direction. Each of the connection portions has a first connection portion length in the first direction and a second connection portion length in the second direction. The first connection portion length is longer than the first gate main portion length. The second connection portion length is shorter than the second gate main portion length. An external connection section is to apply electric power to the gate electrode. A bypass electrode connects the external connection section to each of the connection portions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 2, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Masashi Tanimoto