Patents Examined by Charles N Ausar-El
  • Patent number: 11309300
    Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kil-soo Kim
  • Patent number: 11302534
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes forming a first dielectric layer on a base substrate, the first dielectric layer containing an opening exposing a surface portion of the base substrate; forming an initial gate dielectric layer on the surface portion of the base substrate and on a sidewall surface of the opening in the first dielectric layer; forming a gate dielectric layer by removing a portion of the initial gate dielectric layer from the sidewall surface of the opening, such that a top surface of the gate dielectric layer on the sidewall surface is lower than a top surface of the first dielectric layer; forming a gate electrode on the gate dielectric layer to fill the opening, a portion of the gate electrode being formed on a portion of the sidewall surface of the first dielectric layer; and forming a second dielectric layer on the gate electrode and on the first dielectric layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 12, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11289651
    Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsueh Yang, Shih-Chang Liu, Yuan-Tai Tseng
  • Patent number: 11282801
    Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: March 22, 2022
    Assignee: EV GROUP E. THALLNER GMBH
    Inventors: Viorel Dragoi, Markus Wimplinger
  • Patent number: 11270955
    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Guangxu Li
  • Patent number: 11264540
    Abstract: A light emitting diode includes a light emitting structure including first and second conductive type semiconductor layers and an active layer disposed therebetween, a second hole formed through the active layer and the second conductive type semiconductor layer, and exposing the first conductive type semiconductor layer, a reflective metal layer contacting a portion of the light emitting structure, a cover metal layer contacting at least a portion of the reflective metal layer, a first insulation layer covering the reflective metal layer and the cover metal layer, an electrode layer disposed on the first insulation layer, the electrode layer covering the first insulation layer and filling the second hole, an electrode pad disposed on the light emitting structure, and a first hole formed through the first conductive type semiconductor layer and corresponding to the cover metal layer, in which the electrode pad overlaps the cover metal layer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 1, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Joon Hee Lee, Mi Hee Lee
  • Patent number: 11257808
    Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 22, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yohann Frederic Michel Solaro, Vvss Satyasuresh Choppalli, Chai Ean Gill
  • Patent number: 11257955
    Abstract: The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 22, 2022
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Qinghe Wang, Luke Ding, Leilei Cheng, Jun Bao, Tongshang Su, Dongfang Wang, Guangcai Yuan
  • Patent number: 11251289
    Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11251330
    Abstract: In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: February 15, 2022
    Assignee: CRYSTAL IS, INC.
    Inventors: James R. Grandusky, Leo J. Schowalter, Muhammad Jamil, Mark C. Mendrick, Shawn R. Gibb
  • Patent number: 11227916
    Abstract: According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 18, 2022
    Assignee: Renesas Electronics Corporation
    Inventor: Ryo Kanda
  • Patent number: 11223010
    Abstract: Techniques relate to forming a magnetic tunnel junction (MTJ). A synthetic antiferromagnetic reference layer is adjacent to a tunnel barrier layer. The synthetic antiferromagnetic reference layer includes a first magnetic layer, a second magnetic layer, and a reference spacer layer sandwiched between the first magnetic layer and the second magnetic layer. A magnetic free layer is adjacent to the tunnel barrier layer so as to be opposite the synthetic antiferromagnetic reference layer. The synthetic antiferromagnetic reference layer has a thickness of at least one of 3 nanometers (nm), 4 nm, and 3-4 nm.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guohan Hu, Younghyun Kim, Daniel C. Worledge
  • Patent number: 11211330
    Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 28, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11205713
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
  • Patent number: 11195789
    Abstract: A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventor: Mark K. Hoffmeyer
  • Patent number: 11152312
    Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 11139204
    Abstract: A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11139385
    Abstract: A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Veeraraghavan S. Basker, Huiming Bu
  • Patent number: 11139457
    Abstract: An OLED, a method for fabricating the same, and a display device are disclosed. The OLED includes a first electrode, a first carrier transporting layer, an organic light emitting layer, a second carrier transporting layer, a second electrode, and a light extracting layer between the first electrode and the organic light emitting layer. The light extracting layer is made from a first carrier transporting material. The light extracting layer is formed between the first electrode and the organic light emitting layer at a light exit side of the OLED, and is formed from the first carrier transporting material. This increases the light extracting efficiency of the OLED. The light extracting layer further acts as the first carrier transporting layer, thus simplifying the structure of OLED, making OLED easy to fabricate, and efficiently controlling cost.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xinxin Wang
  • Patent number: 11114549
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ryan Chia-Jen Chen, Ming-Ching Chang, Yi-Chun Chen, Yu-Hsien Lin, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu