Abstract: The present invention provides a thin-film-transistor (TFT) array panel and manufacturing method of the same. The TFT array panel comprises a flexible baseplate, a buffer layer, and a display-element layer. The buffer layer is disposed on the flexible baseplate, a stress-elimination portion is disposed on the buffer layer, the stress-elimination portion is used to eliminate a stress of the flexible baseplate; the display-element layer is disposed on the buffer layer. The present invention is able to decrease the stress of the flexible baseplate, to prevent too large of a stress of the flexible baseplate.

Abstract: A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels.

Abstract: Atomic layer deposition methods for the low temperature deposition of silicon dioxide films having low nitrogen content and low wet etch rates. Silicon dioxide films are deposited and treated with plasma and re-oxidized resulting in low nitrogen content films.

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Abstract: A display device includes: a substrate comprising an active area; data lines extending in a first direction in the active area; scan lines extending in a second direction crossing the first direction in the active area; a plurality of repair lines extending in the first direction or in the second direction in the active area; and a multipath power line comprising a plurality of first wires in the active area and crossing the repair lines, and at least one second wire electrically connected to the first wires and extending in the active area to cross the first wires.

Abstract: A semiconductor device in an embodiment according to the present invention includes a first terminal and a second terminal stacked with a first conductive layer including titanium or molybdenum, a second conductive layer including aluminum above the first conductive layer, and a third conductive layer including titanium or molybdenum above the second conductive layer, a first insulation layer between the first terminal and the second terminal, a second insulation layer between the first insulation layer contacting a side wall part of the first terminal, and a fourth conducing layer extending an upper surface of the first terminal and an upper surface of the second insulation layer. The first terminal and the second terminal are arranged on an exterior side of a drive circuit including a semiconductor element.

Abstract: Integrated circuits, methods for fabricating integrated circuits, and methods for fabricating electrical interconnects for III-V devices are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a III-V device over and/or within a semiconductor substrate. The method further includes forming a conductive layer over the semiconductor substrate and electrically connected to the device. The conductive layer has an upper surface. Also, the method includes forming a plurality of dielectric material areas over the upper surface of the conductive layer to define covered portions and uncovered portions of the upper surface of the conductive layer. The method includes depositing an interconnect metal over the plurality of dielectric material areas and over the uncovered portions of the upper surface of the conductive layer. The interconnect metal is electrically connected to the upper surface of the conductive layer.

Abstract: A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the semiconductor substrate, an interlayer dielectric layer covering the semiconductor device, and a through hole penetrating through the interlayer dielectric layer and a portion of the semiconductor substrate. A metal layer is formed inside the through hole and on a surface of the interlayer dielectric layer. A first planarization process is conducted to remove a portion of the metal layer on the surface of the interlayer dielectric layer. The method also includes conducting an annealing alloy treatment and conducting a second planarization process to completely remove the metal layer on the surface of the interlayer dielectric layer. The manufacturing methods can slowly release stress of the wafer and effectively prevent cracks in silicon vias, thereby reducing TSV leakage problems, thus improving the reliability and yield of the devices.

Abstract: A method of forming a semiconductor device that includes providing a plurality of fin structures, wherein a surface of the fin structures has a first orientation for a diamond shaped epitaxial growth deposition surface. A first epitaxial semiconductor material having a diamond geometry is grown on the diamond shaped epitaxial growth surface. A blocking material is formed protecting a lower portion of the first epitaxial semiconductor material. An upper portion of the first epitaxial semiconductor material is removed to expose a second orientation surface of the first epitaxial semiconductor material for merged epitaxial semiconductor growth. A second epitaxial semiconductor material is epitaxially formed on the first epitaxial semiconductor material. The second epitaxial semiconductor material has a substantially planar upper surface and extends into direct contact with at least two adjacent fin structures.

Abstract: Provided herein is a method including bonding a first oxide layer on a handle substrate to a second oxide layer on a complementary metal oxide semiconductor (“CMOS”), wherein the fusion bonding forms a unified oxide layer including a diaphragm overlying a cavity on the CMOS. The handle substrate is removed leaving the unified oxide layer. A piezoelectric film stack is deposited over the unified oxide layer. Vias are formed in the piezoelectric film stack and the unified oxide layer. An electrical contact layer is deposited, wherein the electrical contact layer electrically connects the piezoelectric film stack to an electrode on the CMOS.

Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.

Abstract: Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF4) and oxygen gas (O2) into the chamber at a temperature of at least about 200° C.

Abstract: A bonding arrangement comprising a silicone-base adhesive composition is suited for temporarily bonding a wafer to a support for wafer processing. The bonding arrangement includes a first temporary bond layer of non-silicone thermoplastic resin, and a second temporary bond layer of thermosetting silicone polymer and/or a third temporary bond layer of thermosetting siloxane-modified polymer. The second and/or third bond layer contains an antistatic agent.

Abstract: A doping process is described, which includes applying to a substrate a film of dopant material that bonds to the substrate by at least one of hydrogen bonding and covalent bonding; encapsulating the film on the substrate with an encapsulant material, and subjecting the encapsulated film to rapid thermal processing to cause dopant from the dopant material to migrate into the substrate.

Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.

Abstract: An organic EL display panel that includes light-reflective electrodes, a red light-emitting layer, a green light-emitting layer, a first blue light-emitting layer, a charge generating layer, a second blue light-emitting layer, and a light-transmissive electrode. In a red sub-pixel region, a first optical length is from 20 nm to 50 nm, and a second optical length is from 210 nm to 230 nm. In a green sub-pixel region, the first optical length is from 20 nm to 50 nm, and the second optical length is from 240 nm to 295 nm. In a blue sub-pixel region, the first optical length is from 20 nm to 60 nm, and the second optical length is from 195 nm to 205 nm.

Abstract: A method of depositing nanowires including generating wells disposed on a patterned conductive film. The patterned conductive film includes well-sites. The patterned conducive film covers a portion of a surface of a substrate. Each of the wells is disposed proximate to a corresponding wellsite. The method includes applying a nanowire mixture to the wells and, after applying the nanowire mixture, at least one nanowire is deposited on a first portion and a second portion of the patterned conductive film by generating an electric field proximate to the patterned conductive film. The first portion and the second portion of the patterned conductive film are separated by a gap.