Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

Abstract: An apparatus and method are described for stacking a plurality of cores.

Abstract: Methods of increasing etch selectivity in imprint lithography are described which employ material deposition techniques that impart a unique morphology to the multi-layer material stacks, thereby enhancing etch process window and improving etch selectivity. For example, etch selectivity of 50:1 or more between patterned resist layer and deposited metals, metalloids, or non-organic oxides can be achieved, which greatly preserves the pattern feature height prior to the etch process that transfers the pattern into the substrate, allowing for sub-20 nm pattern transfer at high fidelity.

Abstract: A semiconductor die package includes first, second and third metal blocks insulated from one another. The first metal block has a thinner inner section, a first thicker outer section at a first end of the thinner inner section and a second thicker outer section at a second end of the thinner inner section opposing the first end. The second metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. The third metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. A semiconductor die has a first terminal attached to the thinner inner section of the first metal block, a second terminal attached to the thinner inner section of the second metal block, and a third terminal attached to the thinner inner section of the third metal block.

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.

Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

Abstract: Transistors each include a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A driver circuit portion includes first to third wirings formed in the same step as the gate electrode, fourth to sixth wirings formed in the same step as the source electrode and the drain electrode, a seventh wiring formed in the same step as a pixel electrode, a first region where the second wiring intersects with the fifth wiring, and a second region where the third wiring intersects with the sixth wiring. The first wiring is connected to the fourth wiring through the seventh wiring. A distance between the wirings in the second region is longer than that in the first region.

Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.

Abstract: The present disclosure provides a method for fabricating a PEDOT:PSS-based electrode, comprising the steps of: preparing a PEDOT:PSS thin film formed on a substrate; treating the thin film with a solution containing 75-100 vol % of sulfuric acid or a sulfuric acid derivative; separating the thin film from the solution and rinsing the separated thin film; and drying the rinsed thin film at a temperature between 60° C. and 160° C. The present disclosure also provides a PEDOT:PSS-based electrode fabricated by the method, and an organic electronic device including the electrode.

Abstract: A pixel unit at a TFT-LCD array substrate includes a thin film transistor, a first storage capacitor, and a second storage capacitor. The first storage capacitor includes a transparent common electrode, a pixel electrode, and a first insulating layer disposed between the transparent common electrode and the pixel electrode. The second storage capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer disposed between the first and second conductive layers. The first conductive layer is connected to the transparent common electrode within the pixel unit. The second conductive layer is connected to the pixel electrode within the pixel unit.

Abstract: The present invention relates to an organic light-emitting element comprising a first electrode, a second electrode, and an organic layer interposed between said first electrode and said second electrode, and to a light-emitting device including the same, wherein in the organic light-emitting element, a connection electrode for electrically connecting two or more elements in serial is formed on a non-light-emitting surface of said organic light-emitting element. The invention can electrically connect a plurality of organic light-emitting elements easily, and can be implemented as a large-scale lighting or display device or the like.

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

Abstract: An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.

Abstract: A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 s. The above method for manufacturing a silicon nitride thin film provides a preferable parameter range and preferred parameters for generating a low-stress SIN thin film at low temperatures, achieves manufacture of a low-stress SIN thin film at low temperatures, and thus, better satisfies the situation requiring a low-stress SIN thin film.

Abstract: Unit pixel cells each includes: a photoelectric conversion film; a transparent electrode; a pixel electrode; an amplification transistor; a reset transistor; and an element isolation STI and a leakage suppression region for electrically isolating the amplification transistor and the reset transistor, the first isolation region being in a silicon substrate, between the amplification transistor and the reset transistor, the reset transistor including: a gate electrode; and a drain region which is connected to the pixel electrode, and is in the silicon substrate, between the gate electrode and element isolation STI and the leakage suppression region, in which a depletion layer formed by a first PN junction between the drain region and its surrounding region and in contact with a surface of the silicon substrate is narrower than a depletion layer formed by a second PN junction between the drain region and its surrounding region and formed in the silicon substrate.

Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer.

Abstract: Various apparatuses and methods are disclosed. An interconnect may include molding material configured to support a light-emitting device, and an electrical trace arranged with the molding material to electrically couple the light-emitting device to a power source, wherein the electrical trace has an electrical insulator on at least a portion thereof. A light-emitting apparatus may include a light-emitting device, molding material supporting the light-emitting device, and an electrical trace arranged with the molding material to electrically couple the light-emitting device to a power source, wherein the electrical trace has an electrical insulator on at least a portion thereof.