Abstract: The present invention discloses a memory access apparatus having address scrambling mechanism that includes an address scrambling circuit and a memory controller. The address scrambling circuit performs the steps outlined below. An original access address is received to be interpreted into original unit indexes and a minimal original unit according to regional unit levels of a memory. Scrambled unit indexes and a minimal scrambled unit are generated correspondingly according to a random address generation algorithm, to further generate a scrambled access address accordingly, in which when a plurality of different original access addresses have at least one the same original unit indexes from the highest block unit level, the scrambled unit indexes generated therefrom are the same. The memory controller accesses the memory according to the scrambled access address.

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.

Abstract: A method, an electronic device, and a computer program product for storage management are provided. The method includes: acquiring a lock attribute record in a lock attribute record chain from a data protection network for backing up data, data protection servers of the data protection network reaching a consensus on the lock attribute record chain, the lock attribute record including a first attribute value of an attribute of a lock operation, the lock operation being used for preventing a backup of the data stored in a storage server from being tampered with; acquiring, based on the lock attribute record, a second attribute value of the attribute of the lock operation from the storage server; and generating, based on determining that the first attribute value does not match the second attribute value, an alarm indicating that the backup is tampered with. This solution can better prevent data from being tampered with.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: Techniques for managing metadata storage units involve: in response to receiving, from a client, a request for allocating a target number of metadata storage units, determining a first number of available metadata storage units remaining in a metadata storage space of a storage system after the allocation is performed; and if the first number is not less than a reserved number, allocating the target number of metadata storage units from the metadata storage space for the client to use, wherein the reserved number is associated with a usage condition of the metadata storage units in the storage system. Accordingly, such techniques can effectively manage metadata and improve the performance of a system.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.

Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

Abstract: Systems and methods are described for efficiently performing various operations at the granularity of a consistency group (CG) within a cross-site storage solution. An example of one of the various operations includes an independent and parallel resynchronization approach that independently brings individual volumes of a CG to a steady state of in-synchronization (InSync), thereby contributing to scalability of CGs by supporting CGs having a large number of member volumes without requiring a change to the resynchronization process. Another example includes preserving dependent write-order consistency when a remote mirror copy goes out-of-synchronization (OOS) for any reason by driving all member volumes OOS responsive to any member volume becoming OOS. Yet another example includes independent creation of snapshots by member volumes to support efficient and on-demand creation by an application of a common snapshots of all or a subset of peered member volumes of a CG with which the application is associated.

Abstract: A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.

Abstract: A method includes creating a deduplicated universal share (US) of data objects, which in turn includes receiving a US of the data objects, deduplicating the US, wherein deduplicating the US includes: hashing segments of the US to generate respective US segment fingerprints; comparing US segment fingerprints to fingerprints for respective segments held in deduplication storage in order to identify segments in the deduplication storage that equate to the US segments, respectively, of the US; storing identifiers that directly or indirectly identify locations, respectively, of the segments, respectively, in the deduplication storage that equate to the US segments, respectively, of the US. After creating the deduplicated universal share, a deduplicated backup of the US is created without reassembling the US from segments held in the deduplication storage, the creating the deduplicated backup including: creating a list that comprises copies of the stored identifiers, and storing the list.

Abstract: In a memory system, a controller writes data of a plurality of clusters into a first memory area via a plurality of channels according to a write command regarding sequential data from a host. The controller specifies the order in which the data of the plurality of clusters is written according to log information and generates order information according to the specified order. The order information is information in which identification information of the cluster and information indicating a writing order are correlated with each other. The controller reads the data of the plurality of clusters from the first memory area according to a read instruction regarding an internal process and rearranges the read data of the plurality of clusters according to the order information. The controller writes the rearranged data of the plurality of clusters into the second memory area via the plurality of channels according to a write instruction regarding the internal process.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A method of controlling a storage device including a command terminal, a plurality of data terminals, and a clock terminal, including receiving a clock signal through the clock terminal; outputting a first status data through the data terminals in accordance with only one of a rising edge and a falling edge of the clock signal in a first transfer mode; outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in a second transfer mode; and receiving and responding to commands via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal while outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in the second transfer mode.

Abstract: Example storage systems, storage devices, and methods provide management of idle time compute tasks from host systems. Storage devices may receive host storage commands for reading and writing host data and host compute commands for executing host compute tasks. Some host compute commands may include a scheduling tag. The storage device may operate in a storage processing state and an idle state and may selectively execute delayed host compute tasks during the idle state.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.