Abstract: A storage device including: a memory storing data based on program modes; and a storage controller including a program mode table, the storage controller configured to: in response to a program request and first data being already stored in the memory, perform a deduplication operation in which the first data is logically and not physically programmed, in response to the program or an erase request, update a count value from a first to a second value, and in response to a determination that a first program mode corresponding to the first value and a second program mode corresponding to the second value are different, transmit a first command and address to the memory such that a first program operation in which the first data programmed with first bits corresponding to the first program mode is re-programmed with second bits corresponding to the second program mode is performed.

Abstract: In a computer system including a distributed file system cluster and a block SDS cluster, the distributed file system cluster has a plurality of distributed file system nodes, and stores a management-subject file redundantly in a plurality of volumes managed by a plurality of distributed file system nodes, the block SDS cluster has a plurality of block SDS nodes, and provides a plurality of the volumes on the basis of storage regions of storage apparatuses of the block SDS nodes, and a CPU of a management server is configured to perform control such that a plurality of the volumes storing the file in the distributed file system cluster for redundancy are not volumes based on a storage region of a storage apparatus of one block SDS node.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine a first value associated with vibrations within an information handling system (IHS); determine that the first value meets or exceeds a first threshold value; after determining that the first value meets or exceeds the first threshold value: receive first data to store via at least one hard disk drive; and store the first data via at least one solid state memory medium; determine a second value associated with vibrations within the IHS; determine that the second value does not meet or exceed the first threshold value; and in response to determining that the second value does not meet or exceed the first threshold value: retrieve the first data from the at least one solid state memory medium; and store the first data via the at least one hard disk drive.

Abstract: A method comprises receiving, in a store buffer, at least a portion of a store instruction, the at least a portion of the store instruction comprising a data operand and a first object capability register operand which comprises a first object type identifier for a first object, obtaining, from a corresponding load instruction, a second object capability register operand which comprises a second object type identifier, and determining whether the first object type identifier matches the second object type identifier.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Abstract: A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register files as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.

Abstract: A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.

Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.

Abstract: An illustrative data storage system captures snapshots of a data structure based on snapshot creation schedules and sets retention periods for the snapshots based on snapshot retention schedules. The data storage system eradicates snapshots based on expirations of the retention periods. In certain examples, the data storage system determines a rule to use to capture a snapshot based on a state of snapshots within one or more lookback periods and/or based on a set of rules each defining a snapshot capture schedule and a snapshot retention schedule.

Abstract: A method to access memory in a physical memory space includes receiving a logical line address (LLA) from a processor, converting the LLA to a physical line address (PLA) and a physical channel address (PCA), and accessing the memory using the PLA and PCA. The memory has multiple memory channels, and multiple memory regions. A memory device may occupy an intersection of a memory region and a memory channel. The conversion includes determining the memory region from the LLA, and determining a region relative address (RRA) from the LLA. The method determines an interleave factor (IF) from the region, and a device line address (DLA) and an uncorrected channel address (UCA) from the RRA and the IF. The method determines the PLA from the DLA and the memory region, and it determines the PCA from the UCA and the memory region.

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

Abstract: A method, computer program product, and computing system for assigning flush ownership for a plurality of containers of a common frozen flushing work set to a storage processor of a pair of storage processors of a storage system. For each container of the plurality of containers of the common frozen flushing work set not assigned to a particular storage processor, the storage space of the container not assigned to the particular storage processor is reclaimed. For each container of the plurality of containers of the common frozen flushing work set assigned to a particular storage processor, data stored in the container assigned to the particular storage processor is flushed to persistent memory of the storage system.

Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Abstract: This document describes aspects of communicating information about repair elements of a memory device. A memory device can include multiple repair elements that can each replace a defective or damaged memory element, such as a memory row, using a repair operation. By knowing a quantity of remaining available repair elements, a user of a memory device can make informed decisions about whether to make a replacement. In operation, a host device can send a command to the memory device requesting repair element information. Logic of the memory device can determine a quantity of repair elements that are available for a repair operation. In some cases, the logic may store this quantity in a register of the memory device. The memory device can signal the quantity of repair elements to the host device in response to the command.

Abstract: A memory device includes memory blocks, a read count storage, a cell counter, and a read reclaim processor. The read count storage stores read count information including read counts of the memory blocks. When a read count of a target block among the memory blocks exceeds at least one threshold count, the cell counter performs a read operation on at least one page among pages included in the target block by using a first read voltage, and calculates a first memory cell count as a number of memory cells read as first memory cells among memory cells included in the at least one page, based on a current sensed from the at least one page in the read operation. The read reclaim processor provides a memory controller with a status code based on the first memory cell count and a number of correctable error bits.

Abstract: A command/address (CA) interface of a memory controller coupled to a memory component is trained (e.g., voltages and timings are adjusted to maximize signal eye opening, sample timing margins etc.) while the CA interface is operated at highest known supported controller PHY frequency. After the CA interface has been trained at highest known supported controller PHY frequency, vendor specific information (e.g., vendor ID number, clock configuration, VDDQ configuration, etc.) is read from the memory component. If the vendor specific information indicates that the CA interface may be operated at a different (e.g., higher) frequency, the memory controller reconfigures its physical interface to operate at the indicated frequency. The memory controller then re-trains its CA interface while operating the CA interface at the indicated frequency.

Abstract: Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.