Patents Examined by Charles Rones
  • Patent number: 10809933
    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 20, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur John Redfern, Asheesh Bhardwaj
  • Patent number: 10810154
    Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Google LLC
    Inventors: Kyle Nesbit, Andrew Everett Phelps
  • Patent number: 10802720
    Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 13, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Chin-Pang Chang, Chun-Yi Lo
  • Patent number: 10802956
    Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 13, 2020
    Assignee: Google LLC
    Inventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
  • Patent number: 10795589
    Abstract: A memory system includes a nonvolatile memory device and a controller circuit. The nonvolatile memory device includes a plurality of physical blocks, each including a storage area which is accessible in units of pages. The controller circuit is configured to control reading and writing of data which are performed on the plurality of physical blocks in units of pages. The controller circuit is also configured to execute a first process on the plurality of physical blocks by performing a second process of reading and a third process of data verification on a first page across each of the plurality of physical blocks and then performing the second process of reading and the third process of data verification on a second page across each of the plurality of physical blocks.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takahiro Masakawa
  • Patent number: 10795590
    Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 6, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventor: Yiren Huang
  • Patent number: 10788996
    Abstract: The present invention effectively utilizes computation resources by allocating the computation resources, in accordance with conditions, to a process that shares a computation resource with another process and a process that occupies a computation resource. Execution control causes a processor core allocated to a storage control process to be occupied by the storage control process, the execution control causes a processor core allocated to an application process to be shared with another process, and the execution control changes the number of processor cores allocated to the storage control process on the basis of I/O information indicating a state of an I/O.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 29, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masakuni Agetsuma, Hiroaki Akutsu, Yusuke Nonaka
  • Patent number: 10782915
    Abstract: A device controller included in a storage device includes a host controller connected to a host memory, a memory controller connected to a plurality of nonvolatile memory devices, a protocol controller configured to control data transfer between the host controller and the plurality of nonvolatile memory devices, and to perform data memory access to a data region of the host memory and non-data memory access to a non-data region of the host memory through the host controller, and a scheduler configured to re-order the data memory access and the non-data memory access such that the non-data memory access to the non-data region is performed after the data memory access to a data chunk has completed, the data chunk being successive data that is allocated within the data region by a physical region page (PRP).
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Bong Kim, Jun-Young Jang, Jong-Hwan Kim, Ho-Jun Shim
  • Patent number: 10783086
    Abstract: A method for accessing data is provide, the method includes: receiving a first address and identification information used to identify an address type; and when the identification information indicates a logical address type, converting the first address into a first physical address, and accessing at least one corresponding flash memory chip in the storage device; or when the identification information indicates a physical address type, directly accessing at least one corresponding flash memory chip in the storage device. When the storage device is accessed, a type of an accessed address is determined according to the identification information. If the address is a logical address, the storage controller maps the logical address to a physical address and accesses the physical address; or if the address is a physical address, the storage controller directly accesses the physical address sent by the host.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 22, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Zhou, Guanghui Liu, Weiye Zhang
  • Patent number: 10776038
    Abstract: In one embodiment, a system includes one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including sequencing a plurality of rows into a first sequence based on a first criteria and determining to store a first set of the plurality of rows in a first block of a first storage unit in accordance with the first sequence. The operations further include determining to store, in a first block of the second storage unit, a block identification of the first block of the first storage unit and a row identification for each row of the first set of the plurality of rows. The operations further include re-creating the first set of the plurality of rows of the first block of the first storage unit using information stored in the second storage unit.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 15, 2020
    Assignee: Bank of America Corporation
    Inventor: Sandeep Verma
  • Patent number: 10776007
    Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Masaki Miyagawa, Hiroshi Nozue, Kazuhiro Kawagome, Hiroto Nakai, Hiroyuki Sakamoto, Tsutomu Owa, Tsutomu Unesaki, Reina Nishino, Kenichi Maeda, Mari Takada
  • Patent number: 10776148
    Abstract: Disclosed are systems and methods for parallel processing an input data set. During a map stage of a computation, starting with a first virtual machine (VM) acting as a parent VM and an input data set, the system clones the parent VM to generate at least one linked clone child VM. The system further divides the input data set into a first chunk for the parent VM and a second chunk for the at least one child VM by determining a starting pointer for each chunk. Each chunk is processed by a VM to generate an intermediate data result, which is stored in a network storage device. The plurality of VMs then perform a reduce stage on the plurality of intermediate data results stored in the network storage device.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 15, 2020
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10768827
    Abstract: Methods, systems, apparatuses, and computer program products are provided that enable storage performance to be customized and throttled at the drive level. For example, performance metric(s) may be specified for virtual drive(s) assigned to a virtual machine. Physical storage disk(s), which are mapped to the drive(s), may be allocated based on the specified performance metric(s). By providing a means to customize and throttle on a per-drive basis, each function of the virtual machine can be provided a dedicated channel for input/output transactions, thereby ensuring that no function is starved of resources.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: September 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Harshad Nadkarni
  • Patent number: 10761732
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: obtaining a usage status of a first physical unit of a rewritable non-volatile memory module for storing data from a host system; determining a first rule according to the usage status; and performing a first operation according to the first rule. The first operation includes: storing a first data from the host system into the first physical unit; and storing a second data from the rewritable non-volatile memory module into a second physical unit, where the first rule corresponds to a first ratio between a data volume of the first data and a data volume of the second data. Accordingly, the memory storage device can store external and internal data stably.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: September 1, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Wen Hsiao, Hsueh-Chi Lu
  • Patent number: 10761985
    Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10747659
    Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retrieval. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Weijie Yu, Rohit Sehgal, Zachary David Shepard
  • Patent number: 10747677
    Abstract: A storage system comprises a plurality of storage devices and an associated storage controller. The plurality of storage devices are configured to store a plurality of logical units (LUNs) and snapshot data structures associated with the plurality of LUNs. The storage controller is configured to determine a mapping of a logical address associated with a pending read or write operation to a snapshot address associated with a given snapshot data structure of the storage system that comprises a plurality of nodes generated during point-in-time snapshots taken based on at least one of the LUNs, lock at least a portion of the given snapshot data structure during the read or write operation based on the determined mapping, and release the lock on the at least a portion of the given snapshot data structure in response to a completion of the read or write operation.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran
  • Patent number: 10740032
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Chiranjeev Acharya, Sean James Salisbury, Eduard Vardanyan, Arthur Brian Laughton
  • Patent number: 10740244
    Abstract: A memory system includes a first and a second flash domain, a domain distributor, and a first redirector. The first and second flash domains includes first and second spare memory dies, respectively. The domain distributor is configured to generate a first logical address corresponding to first data and to generate a second logical address corresponding to second data. The first redirector is configured to receive the first data and the second data from the domain distributor and to respectively provide the first data and the second data to the first flash domain and the second flash domain. The first redirector is configured to provide a part of the second data corresponding to a first fail memory die to the first flash domain, if the second flash domain include the first fail memory die, such that the first redirector replaces the first fail memory die with the first spare memory die.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sil-wan Chang
  • Patent number: 10732851
    Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM modules, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 4, 2020
    Assignee: CORIGINE (HONG KONG) LIMITED
    Inventors: Hillel Gazit, Sohail Syed, Gevorg Torjyan