Patents Examined by Charles Rones
  • Patent number: 10318177
    Abstract: A method includes creating multiple logical compartments in a data storage device to hold respective multiple portions of an ordered list of elements, encapsulating each element, of a portion for each compartment, in a node with pointers to successive nodes in the portion, creating a set of references to a first node in each compartment, and providing a count of the number of elements in each compartment.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SAP SE
    Inventor: Arjun Krishnakumar
  • Patent number: 10310752
    Abstract: Techniques for allocating mapped RAID extents of a RAID group may include: determining a pool of N physical storage devices; selecting M physical storage portions, wherein each of the M physical storage portions is selected from a different one of the N physical storage devices of the pool; and allocating a first mapped RAID extent as the selected M physical storage portions. The first mapped RAID extent may denotes a stripe of the RAID group. Physical storage portions for each mapped RAID extent may be selected from the N physical storage devices with a goal of maintaining even distribution of the selected portions among the N physical storage devices. Such selection may use a neighborhood matrix and a subset of all possible combinations of M physical storage devices that may be selected from the N physical storage devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 4, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne Li, Geng Han, Jian Gao, Jibing Dong, Jianbin Kang, Lili Chen
  • Patent number: 10310748
    Abstract: This specification describes methods, systems, and computer program products for maintaining data representing where each data block of multiple data blocks are stored among multiple computing nodes. Each computing node generates a respective locality summary based on locally stored data blocks, and submits the locality summary to a controlling computing node.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 4, 2019
    Assignee: Pivotal Software, Inc.
    Inventors: Harshad Deshmukh, Adalbert Gerald Soosai Raj, Jignesh M. Patel
  • Patent number: 10310772
    Abstract: The present disclosure provides memory control methods and memory control apparatus. An exemplary method includes providing a memory having a targeted memory zone, the targeted memory zone having a plurality of memory cells, and a storage capacity of each memory cell being one page; receiving and reading out to-be-stored data and obtaining the targeted address information of the to-be-stored data; reading out data status of all memory cells of a targeted memory zone; determining the data status of the memory cells of the targeted memory zone; performing a programming operation to a memory cell with an erased state to write the to-be-stored data into the memory cell with the erased state; and performing an erasing operation to a memory cell having a logic address of written data to remove the logic address.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Shi Cong Zhou
  • Patent number: 10303388
    Abstract: Management of access to data stored in a storage system is provided using container images. Specifications for a requested data scan of the storage system are received. The requested data scan is performed using a container image according to the received specifications, the container image being run on the storage system. A cost of resources is associated with the requested data scan performed using the container image. Access to data stored in the storage system is managed based on the cost of resources.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 28, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Amit Lieberman, Jehuda Shemer, Assaf Natanzon, Leehod Baruch, Ron Bigman
  • Patent number: 10303371
    Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to an external device, and a control circuit. The control circuit is configured to carry out over an elapsed time period first write operations to write data received through the communication interface in the nonvolatile memory, second write operations to write data stored in a memory region of the nonvolatile memory to another memory region of the nonvolatile memory, and wait operations during which no data are written, read, or erased in the nonvolatile memory, such that the wait operations are carried out during a smaller percentage of the elapsed time period as the elapsed time period becomes longer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takamasa Hirata
  • Patent number: 10296258
    Abstract: Offloading data storage to a decentralized storage network, including: identifying a plurality of decentralized storage networks that the storage system can utilize for storing data; selecting, in dependence upon characteristics of each decentralized storage network and requirements associated with storing the data, one or more decentralized storage networks for storing the data; and initiating storage of the data on the selected one of more decentralized storage networks.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 21, 2019
    Assignee: Pure Storage, Inc.
    Inventor: Michael Richardson
  • Patent number: 10296480
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim, Tae Ho Kim
  • Patent number: 10289569
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Patent number: 10289349
    Abstract: A local storage device (LSD) is provided configured to have a host device (HD) in communication with the LSD. The LSD includes a memory array. The LSD is configured to characterize data access usage of the LSD by at least one program executing on the HD. The LSD is configured to monitor access to the LSD as a result of data access operations by the HD relative to the memory array of the LSD. The LSD is additionally configured to determine characteristics of the monitored access. The LSD is additionally configured to, based on characteristics of the monitored access, determine and store data on the LSD indicative of the characterized monitored access.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 14, 2019
    Assignee: SanDisk IL, LTD.
    Inventors: Alain Nochimowski, Micha Rave, Itzhak Pomerantz, Eitan Mardiks
  • Patent number: 10289329
    Abstract: A method, data processing system and program product utilize dynamic logical storage volume sizing for burst buffers or other local storage for computing nodes to optimize job stage in, execution and/or stage out.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, David L. Hermsmeier, Jin Ma, Gary J. Mincher, Bryan S. Rosenburg
  • Patent number: 10289550
    Abstract: A method for dynamic write-back cache sizing in solid state memory storage. The method includes receiving a request to write a data fragment to a memory location of a storage medium, identifying a resource required for the writing, and obtaining a state of the resource. The state of the resource is governed by a number of data fragments that are stored in the write-back cache which require the resource. The number of data fragments in the write-back cache which require the resource are limited to enable writing of all data fragments in the write-back cache to the storage medium, within a specified amount of time. The method further includes determining that the state of the resource allows the received data fragment to be stored in the write-back cache, and based on the determination: storing the data fragment in the write-back cache and acknowledging the write request.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Richard H. Van Gaasbeck
  • Patent number: 10275162
    Abstract: Methods and systems that may be implemented for managing data migration from relatively higher performance and higher endurance solid state non-volatile memory media to relatively lower performance and lower endurance solid state non-volatile memory media. The disclosed methods and systems may be implemented to reduce write amplification that occurs to solid state non-volatile memory media of a memory device by using frequency of LBA update as a parameter for controlling and optimizing data eviction from a relatively higher performance and higher endurance input buffer section in the receiving front of a memory device to a relatively lower performance and lower endurance main memory section of the same memory device.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Dell Products L.P.
    Inventors: Lip Vui Kan, Young Hwan Jang
  • Patent number: 10268580
    Abstract: Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Namakkal N. Venkatesan, Ren Wang, Andrew J. Herdrich
  • Patent number: 10268598
    Abstract: A counter of a primary memory module provides a count indicative of the number of times the primary memory module has ever been read/written by a processor. With the count, an operating mode of the primary memory module is evaluated to optimize memory allocation performed by the data processing system, adjust the operating mode of the primary memory module, and send a warning message to a user, for example.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chang Li Ping, Alpus P. Chen, Chun-Wei Chen, Elysee Hsieh, Kelvin Shieh, Wei-Chin Tsai
  • Patent number: 10268400
    Abstract: A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinaaanangur Ravimohan, Muralitharan Jayaraman
  • Patent number: 10254962
    Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Steven M. Partlow, Thomas F. Rankin, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 10254968
    Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM module, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 9, 2019
    Assignee: FIRQUEST LLC
    Inventors: Hillel Gazit, Sohail Syed, Gevorg Torjyan
  • Patent number: 10248444
    Abstract: A method for allocating virtual machines (VMs) to run within a non-uniform memory access (NUMA) system includes a first processing node and a second processing node. A request is received at the first processing node for additional capacity for at least one of (a) establishing an additional VM and (b) increasing processing resources to an existing VM on the first processing node. In response to receiving the request, a migration manager identifies whether the first processing node has the additional capacity requested. In response to identifying that the first processing node does not have the additional capacity requested, at least one VM is selected from an ordered array of the multiple VMs executing on the first processing node. The selected VM has low processor and memory usage relative to the other VMs. The selected VM is migrated from the first processing node to the second processing node for execution.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 2, 2019
    Assignee: Dell Products, L.P.
    Inventors: Kiran Kumar Devarapalli, Krishnaprasad K, Shiva Prasad Katta
  • Patent number: 10241864
    Abstract: A method and system for expanding a set of storage units. Expanding a set of storage units includes facilitating storage of a set of encoded data slices in a set of storage units within a first time frame. When detecting expansion of the set of storage units with new storage units within a second timeframe, primary storage units of the expanded set of storage units based are identified based on a write threshold value associated with the expanded set of storage units. For each new primary storage unit, storage of an imposter encoded data slice sourced from another storage unit that is not a primary storage unit but holds an encoded data slice of the set of encoded data slices is facilitated. The other storage unit then deletes the imposter encoded data slice.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Ravi V. Khadiwala, Jason K. Resch, Ilya Volvovski, Ethan S. Wozniak