Patents Examined by Charles Rones
  • Patent number: 11327656
    Abstract: A method for accessing a dynamic memory module, the method may include (i) receiving, by a memory controller, a set of access requests for accessing the dynamic memory module; (ii) converting the access requests to a set of commands, wherein the set of commands comprise (a) a first sub-set of commands that are related to a first group of memory banks, and (b) a second sub-set of commands that are related to a second group of memory banks; (iii) scheduling, by a scheduler of the memory controller, an execution of the first sub-set; (iv) scheduling an execution of the second sub-set to be interleaved with the execution of the first sub-set; and (v) executing the set of commands according to the schedule.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 10, 2022
    Assignee: Mobileye Vision Technologies Ltd.
    Inventors: Boris Shulman, Yosef Kreinin, Leonid Smolyansky
  • Patent number: 11327939
    Abstract: A method for indexing dirty data in a storage system page includes: obtaining a point quantity of storage points in the storage page and dirty data distribution information; creating a bitmap based on the point quantity and dirty data distribution information; creating an extended segment set based on the dirty data distribution information, and obtaining the number of current extended segments in the extended segment set; obtaining, according to the point quantity, a first storage cost for indexing dirty data using the bitmap in the target storage page; obtaining, according to the number of current extended segments and the segment capacity, a second storage cost for indexing dirty data using the extended segments in the target storage page; and determine, according to the first storage cost and the second storage cost, to index the dirty data in the target storage page by means of the bitmap or the extended segments.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 10, 2022
    Assignee: ZTE CORPORATION
    Inventors: Shengmei Luo, Jiwu Shu, Youyou Lu, Hongzhang Yang
  • Patent number: 11327889
    Abstract: The invention relates to a method for managing a buffer memory space associated with a persistent data storage system of a computing machine. The buffer memory space is suitable for temporarily storing in the RAM of the machine one or more portions of a single data file of the persistent data storage system that was previously accessed by one or more processes executed on the machine. The operating system of the machine tracks each of the portions of the file that are projected in the buffer memory space by a descriptor belonging to a plurality of buffer memory projection descriptors which are all associated with the tracking of one or more portions of the file projected in the buffer memory space.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 10, 2022
    Assignee: BULL SAS
    Inventors: Jean-Olivier Gerphagnon, Frédéric Saunier, Grégoire Pichon
  • Patent number: 11320987
    Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Wei Wang, Jiangli Zhu, Ying Yu Tai
  • Patent number: 11321273
    Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: Google LLC
    Inventors: Kyle Nesbit, Andrew Everett Phelps
  • Patent number: 11314460
    Abstract: A solid state drive (SSD) enabled to process and store block addressable and byte addressable data, includes a first storage region for storing byte addressable data, a second storage region for storing block addressable data, and an SSD controller coupled to the first storage region and the second storage region by a bus. The SSD controller includes a processor and an interface for receiving data packets from a host. The SSD controller receives a data packet from the host at the interface, determines whether the data packet includes byte addressable data or block addressable data at the processor, selects either the first storage region or the second storage region based on the determination, and stores the data associated with the data packet in the selected storage region.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 26, 2022
    Assignee: Kioxia Corporation
    Inventors: Edward Xiao, Scott Stetzer
  • Patent number: 11314442
    Abstract: A method for determining to rebuild a namespace. The method includes one or more computer processors identifying a set of storage devices associated with the namespace of the user. The method further includes determining a state of health of a namespace based on information related to the set of storage devices associated with the namespace and further includes identifying a set of criteria related to the state of health of the namespace. The method further includes responding to determining that one or more criteria related to the state of health of namespace attains respective trigger values by replacing a first set of storage devices that store data corresponding to the namespace and are included among one or more storage systems. The method further includes dictating to replace the first set of storage devices that store data corresponding to the namespace and are included among the one or more storage systems.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Asimuddin Kazi, Ethan Wozniak
  • Patent number: 11314449
    Abstract: In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Derek Alan Sherlock
  • Patent number: 11307990
    Abstract: Implementations of the present specification provide a method for deploying a smart contract. According to one implementation the method includes: receiving a transaction request for invoking a first contract; obtaining a first instruction code and a function index table, wherein the function index table is used to indicate a memory address of an instruction code corresponding to each of import and export functions in the first contract; determining a first memory address corresponding to the invocation function based on the function index table; and executing the first instruction code in the first memory address based on the determined first memory address.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 19, 2022
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Zhongxiao Yao
  • Patent number: 11301378
    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 12, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Christopher Haywood
  • Patent number: 11294817
    Abstract: To perform a lookup for a group of plural portions of data in a cache together, a first part of an identifier for a first one of the portions of data in the group is compared with corresponding first parts of the identifiers for cache lines in the cache, the first part of the identifier for the first one of the portions of data in the group is compared with the corresponding first parts of the identifiers for the remaining portions of data in the group of plural portions of data, and a remaining part of the identifier for each portion of data is compared with the corresponding remaining parts of identifiers for cache lines in the cache. It is then determined whether a cache line for any of the portions of data in the group is present in the cache, based on the results of the comparisons.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: April 5, 2022
    Assignee: Arm Limited
    Inventor: Antonio Garcia Guirado
  • Patent number: 11294818
    Abstract: Techniques perform data storage. Such techniques may involve writing metadata to a first cache of a first processor, the metadata indicating allocation of a storage resource to user data. Such techniques may further involve determining an address range of the metadata in the first cache. Such techniques may further involve copying only data stored in the address range in the first cache to a second cache of a second processor. Accordingly, the data transmission volume between two processors is reduced, which helps to improve the overall performance of a storage system.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 5, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Yousheng Liu, Geng Han, Jian Gao, Ruiyong Jia, Jianbin Kang
  • Patent number: 11287977
    Abstract: Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: March 29, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kenichi Betsuno, Takashi Nagao, Yuusaku Kiyota, Tomohiro Yoshihara
  • Patent number: 11288202
    Abstract: Provided herein may be a memory controller configured to control a memory device. The memory controller may include: a mapping data determination unit configured to receive, from a memory device, bitmap information indicating whether a map segment, corresponding a bit included in the bitmap information and including a plurality of pieces of extended mapping data, has been stored in the memory device and a mapping data management unit configured to output information about generation of the plurality of pieces of extended mapping data based on the bitmap information. Each of the plurality of pieces of extended mapping data may include mapping information between a logical block address and a physical block address.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11288010
    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 29, 2022
    Assignee: INTEL CORPORATION
    Inventors: Zhi Yong Chen, Zhiqiang Qin, Xueyan Wang, Fang Yuan
  • Patent number: 11288185
    Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 29, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Kuo-Ting Huang
  • Patent number: 11288196
    Abstract: In response to receiving a read metadata request from the host system for a data portion, the storage system may determine a status and location of the data portion, including determining whether the data portion is in a cache of the storage system. If the data portion is in the cache, the storage system may send a response that includes the data portion itself along with the status and location of the data portion. If the data portion is not in the cache, the storage system may send a response to the read metadata request that includes the status and location of the data portion, but not the data portion itself. The host system may be configured to determine whether the data portion has been returned with the metadata response, and if so, refrain from sending a separate data request, for example, to retrieve the data portion from cache.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Ian Wigmore, Arieh Don
  • Patent number: 11281406
    Abstract: A memory system includes a semiconductor storage device in an embodiment that performs transfer of a command, an address, and transfer data excluding the command and the address between a controller and a nonvolatile memory. The controller and the nonvolatile memory transfer the command and the address in synchronization with a capturing signal during writing and readout, transfer the transfer data in synchronization with a synchronous control signal, and transfer the command, the address, and the transfer data in synchronization with the capturing signal during function setting for the nonvolatile memory.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Kioxia Corporation
    Inventor: Naoaki Kanagawa
  • Patent number: 11281981
    Abstract: A storage system and sorting-based method for random read command prediction in a multi-queue system are provided. In one embodiment, a method for command prediction is performed in a storage system comprising a memory and being in communication with a host. The method comprises receiving a read command sequence from the host, wherein read commands in the read command sequence originate from a plurality of command queues in the host such that read commands in the read command sequence received from the host are out of order; sorting read commands in the read command sequence received from the host based on logical block addresses; and predicting a next read command from the sorted read commands. Other embodiments are provided.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Ariel Navon, Shay Benisty
  • Patent number: 11281608
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis