Patents Examined by Charles Rones
  • Patent number: 11797231
    Abstract: Methods, systems, and devices for hazard detection in a multi-memory device are described. A device may receive a first command that indicates a first bank address, a first row address, and a first column address. Based on the first bank address, the device may select a buffer for a hazard detection procedure that detects hazardous commands. The device may compare, as part of the hazard detection procedure, the first row address and the first column address from the first command with a second row address and a second column address from a second command in the buffer. The device may determine whether the first command and the second command are hazardous commands based on comparing the first row address and the first column address from the first command with the second row address and the second column address from the second command.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Taeksang Song, Saira Samar Malik, Chinnakrishnan Ballapuram
  • Patent number: 11798627
    Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 24, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sergey Anatolievich Gorobets, Xinmiao Zhang, James Fitzpatrick
  • Patent number: 11797178
    Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: October 24, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ramesh Chandra Chaurasiya, Sanish N. Suresh, Clarete Riana Crasta, Sharad Singhal, Porno Shome
  • Patent number: 11797452
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: October 24, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Patent number: 11789611
    Abstract: The disclosed technology relates to managing input-output operation in a zoned storage system includes identifying a first physical zone and a second physical zone within a zoned namespace solid-state drive associated with a logical zone to perform a received write operation. Data to be written in the received write operation is temporarily staged in a zone random write area associated with the identified second physical zone. Based a storage threshold of the zone random write area, a determination is made regarding when to transfer temporarily staged data to be written area to the identified second physical zone. When the storage threshold of the zone random write area determined to have exceeded, temporarily staged data to be written is transferred to the identified second physical zone.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 17, 2023
    Assignee: NETAPP, INC.
    Inventors: Rohit Shankar Singh, Douglas P. Doucette, Abhijeet Prakash Gole, Prathamesh Deshpande
  • Patent number: 11789822
    Abstract: The present disclosure describes techniques for implementing fast and reliable metadata operations. A metadata area instance may be created in a persistent memory associated with a host. The metadata area instance may comprise a first portion configured to store an initial state of metadata, a second portion configured to store an actual state of the metadata, and a third portion configured to store a plurality of modifications to the metadata. A main copy of the metadata may be generated by performing write operations in the metadata area instance. The main copy of the metadata may be updated based on receiving information indicative of a modification to the metadata.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 17, 2023
    Assignees: LEMON INC., BEIJING YOUZHUJU NETWORK TECHNOLOGY CO. LTD.
    Inventors: Viacheslav Dubeyko, Jian Wang
  • Patent number: 11782602
    Abstract: Systems and methods described herein provide for determining priority levels within one or more data streams established between a host computing device and a storage device. Data streams that have been assigned a sufficiently high priority may be provided additional processing resources available within the storage device. These additional processing resources may include an increased number of write buffers, superblocks, and access to other ancillary resources that facilitate an increased level of performance compared to data streams not provided additional processing resources. The assignment of priority to the data streams can occur through the use of one or more priority identifiers. Many types and scales of priority identifiers may be used. The establishing of this system of priority identifiers can occur by the storage device notifying the hose of the accepted priority identifier usage. In other embodiments, the storage device may come preconfigured with a priority indication system and scale.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ravishankar Surianarayanan
  • Patent number: 11775192
    Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: October 3, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 11775449
    Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: October 3, 2023
    Inventors: Nadav Grosz, Jonathan Scott Parry
  • Patent number: 11775426
    Abstract: A memory system includes a memory device including plural memory blocks and a controller configured to perform garbage collection on a victim block among the plural memory blocks. The controller is further configured to stop the garbage collection in response to an interrupt and invalidate a valid data item, which is copied from the victim block to a target block during the garbage collection.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventor: Dong Young Seo
  • Patent number: 11775212
    Abstract: A data storage device includes a first memory device storing first data; a second memory device including a first zone storing second data, a second zone storing third data, and a third zone storing fourth data; a storage; and a controller in communication with the first memory device, the second memory device, and the storage and configured to receive one or more requests from a host and control an input and output of data from and to the first memory device, the second memory device, and the storage in response to the one or more requests from the host. The controller is further configured to copy a portion of the first data read from the first memory device to the first zone, copy a portion of the second data read from the first zone to the second zone, copy a portion of the third data read from the second zone to the third zone, and store data read more than a set number of times among data stored in the first memory device and the second memory device in the third zone.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 3, 2023
    Assignee: SK HYNIX INC.
    Inventor: Da Eun Song
  • Patent number: 11775210
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Patent number: 11775442
    Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 3, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Monish Shantilal Shah, John Grant Bennett
  • Patent number: 11768603
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Patent number: 11768629
    Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Nadav Grosz, Roberto Izzi, Jonathan S. Parry
  • Patent number: 11762596
    Abstract: A computer system having a host in communication with a data storage device is coupled to the host via a peripheral bus and a host interface. The data storage device has a controller, non-volatile storage media; and firmware containing instructions configures the operations of the controller. The host transmits a sequence of commands to the storage device to read data items from, or write data items to, the non-volatile storage media. The storage device examines a subset of the commands to determine whether or not data items identified in the subset are addressed sequentially and optimizes processing of at least a portion of the sequence of commands based on a result of a determination of whether or not data items identified in the subset are addressed sequentially.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11755255
    Abstract: A memory device includes a plurality of memories, a plurality of access units, and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit. A resistor can be shared by the plurality of memories for impedance matching, which can shorten calibration time.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 12, 2023
    Assignee: SK hynix Inc.
    Inventors: Won Ha Choi, Oung Sic Cho, Jong Hoon Oh
  • Patent number: 11755251
    Abstract: A system includes a virtual computational storage emulation module configured to provide a virtual computational storage device. The system further includes a storage element, where the virtual computational storage emulation module is configured to store data associated with the virtual computational storage device at the storage element. The system further includes a compute element. The virtual computational storage emulation module is configured to send a compute request associated with the virtual computational storage device to the compute element.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: September 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gayathiri Venkataraman, Vishwanath Maram, Matthew Shaun Bryson
  • Patent number: 11755515
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 11748264
    Abstract: Obtaining an approximate unique count for a column from a table from a database includes, generating, for a value from an unevaluated row, a hash value in a defined range of hash values, determining a cardinality of leading zeros in the hash value, identifying a bucket with respect to the hash value from a plurality of buckets corresponding to the defined range of hash values, wherein the buckets from the plurality of buckets correspond with respective non-overlapping portions of the defined range of hash values, such that the hash value is in the portion of the defined range of hash values corresponding to the bucket, and appending to an unsorted sparse representation a bucket identifier for the bucket and the cardinality of the leading zeros, and, in response to a determination that unevaluated rows are unavailable in the table, determining the approximate unique count using the unsorted sparse representation.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: September 5, 2023
    Assignee: ThoughtSpot, Inc.
    Inventors: Ashok Anand, Bhanu Prakash, Tushar Marda