Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

Abstract: A high frequency transferred electron device having electron ballistic injection and extraction for very high efficiency is disclosed. The device comprises a semiconductor body having at least two electrodes with a thin barrier layer being formed at one electrode for launching ballistic electrons at a controlled kinetic energy into the body. The body includes a drift region having a low, controlled density of electrons and impurities. A second heavily doped (N+) collector semiconductor layer at the second electrode insures that there is no barrier at the second electrode interface, thereby allowing energetic electrons to be removed from the drift region and allowing entry of new ballistic electrons to improve the efficiency and frequency response of the device.

Abstract: The thermal behavior of a semiconductor body is considerably improved by giving parts of high and equal dissipation the same surface area and situating these regions so that the edge of the semiconductor body constitutes a mirror surface for a row of such regions. These regions may comprise subtransistors of power transistors or a Darlington circuit. In the latter case, a further improvement is possible by thermal cross-coupling. The additional space at the edge which is required to apply the reflection principle can be used for nondissipating elements.

Abstract: A semiconductor memory device having a floating gate transistor and an insulated gate transistor, is provided a p-type semiconductor substrate, first, second and third semiconductor regions which are formed in the surface area of the substrate, a floating gate electrode capacitively coupled through a first insulating layer to a current path including the first and second semiconductor regions, a control gate electrode capacitively coupled through a second insulating layer to the floating gate electrode, and an insulated gate electrode which is formed through a first insulating layer on that portion of the substrate which lies between the second and third semiconductor regions. The first insulating layer of the semiconductor memory device is formed on that portion of the substrate which lies between the first and second semiconductor regions. The control gate electrode is a fourth semiconductor region which is formed in the surface area of the substrate.

Abstract: The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

Abstract: A P type buried layer which is buried in an N type low resistance substrate is formed directly through a diffusion after which an N type buried layer is formed through a diffusion. Thereafter, an N type high resistance layer is epitaxially grown on the entire area of the upper surface thereof.

Abstract: A sidewall isolation structure for field effect transistor which includes a first electrical insulating layer and a second electrical insulating layer contiguous with the first layer. The second electrical insulating material is etched above or below the surface level of the first insulating layer to provide recesses in the sidewall isolation structure, and method for the preparation thereof.

Abstract: The soft-error in an MOS d-RAM can be reduced by an impurity-doped region having a conductivity opposite to that of a substrate. The impurity-doped region is formed in the substrate and below and in contact with a field oxide layer formed on the substrate, for collecting minority carriers produced by incident radiation. A storage capacitor is formed on the field oxide layer for shielding the minority carriers. This device has the further advantage of not decreasing the density of a memory cell array.

Abstract: A lateral double-diffused MOS transistor includes an intermediate semiconductor layer of the same conductivity type as the channel region which extends laterally from the channel region to beneath the drain contact region of the device. This intermediate semiconductor layer substantially improves the punchthrough and avalanche breakdown characteristics of the device, thus permitting operation in the source-follower mode, while also providing a compact structure which features a relatively low normalized "on" resistance.

Abstract: An IC having closely packed rows of cells enables both regular structures (register stacks and memories) and random logic structures to be efficiently fabricated from it. Circuits having more parallel-to-the-length-of-the-rows interconnecting wiring than regular structures have wiring corridors over inactive rows of cells whose cells are not connected into the circuit. A grid power bus structure smooths power flow with a minimum of active device loss by hyphenating "large" cells across the cell-row-crossing conductors.

Abstract: A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.

Abstract: A p.sup.- -type well region is formed in a n.sup.- -type semiconductive substrate. An n-channel metal oxide semiconductor field effect transistor (N-MOSFET) is formed in the p.sup.- -type well region. The p.sup.- -type well region is electrically insulated from an external potential such as the ground potential. The gate electrode of the N-MOSFET is connected to the p.sup.- -type well region. When the N-MOSFET is used as an input protective device of a CMOS integrated circuit, an n.sup.+ -type layer corresponding to the source electrode of the N-MOSFET is grounded, while another n.sup.+ -type layer corresponding to the drain electrode thereof is connected to an input terminal of the CMOS integrated circuit through a resistor.

Abstract: A semiconductor memory device comprising a semiconductor substrate of one conductivity type, memory cells each including a semiconductor impurity region of a conductivity type opposite to that of the substrate formed in the semiconductor substrate, a charge storage portion formed in the semiconductor substrate, and a gate portion to form a channel in the semiconductor substrate between the semiconductor impurity region and the charge storage portion, and a metal conductive layer. In order to reduce soft errors of the memory device caused by alpha particles from package materials, the metal conductive layer overlaying the charge storage portion is formed so as to have a width greater than the minimum width used in an integrated circuit at a portion thereof overlaying the substantial part of the charge storage portion.

Abstract: A Hall effect device for responding to weak magnetic fields uses a small chip of gallium arsenide located between the overlapped ends of two flux concentrators. The spacing between the concentrators may be as small as 95 micrometers. The flux concentrator, which serve to enhance the device's sensitivity are made of amorphous magnetic material, i.e. a metallic glass, which has high permeability.

Abstract: The present invention consists in a semiconductor integrated circuit device characterized in that a circuit programming wiring layer is formed on an insulating film which is provided on a semiconductor substrate, and that a light shielding protective mask material is deposited around the circuit programming wiring layer except a program part thereof, through an insulating film.

Abstract: A segmented semi-insulating polysilicon (SIPOS) layer is used between conductors making contact to the surface of a silicon device in order to shield the surface from the effects of charge on dielectric layers above the surface so as to maintain breakdown voltages. The segmenting of the SIPOS layer significantly increases the resistance thereof and thereby limits leakage generated by the layer.

Abstract: A first ROM is comprised of a transistor matrix. The polycrystalline silicon forming the gates of the transistors of the first ROM and another polycrystalline silicon region are arranged in a matrix, and diodes are formed by PN junctions at the crossing points. Thus, a second ROM is comprised of a diode matrix. The two ROMS are formed in layers on one common plane and each ROM can retain different information, independently of each other.

Abstract: A semiconductor device embodying this invention comprises a first conductive layer deposited on a semiconductor substrate to form a first element; a second conductive layer constituting a second element; and a third conductive layer superposed on the second conductive layer with an insulation layer interposed between said second and third conductive layers to form a third element. Only the second conductive layer formed from portions of the same layer of a conductive material is oxidized to provide an insulation layer; and consequently the first conductive layer is made thicker than the second conductive layer.

Abstract: A two terminal monolithic integrated clamp circuit includes first and second circuits coupled between the two input terminals thereof for clamping the voltage appearing across the two terminals to a predetermined voltage. The first circuit is responsive to the voltage level appearing at the first terminal exceeding the voltage level at the second terminal by said predetermined amount for clamping the voltage level thereat while shunting the majority of the current through the clamping circuit to substrate ground of the integrated circuit. The second circuit is responsive to the voltage level appearing at the second terminal exceeding the voltage level at the first terminal by said predetermined amount for clamping the voltage thereat while shunting the majority of the current to substrate ground.