Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.

Abstract: The mobility of carriers in the channel region of a field effect transistor can be increased by providing a layered structure wherein electrons are separated from impurities. The channel is made up of external layers of wide bandgap material and internal layers with a narrower bandgap where the bottom of the conduction band of one layer is below the top of the valence band of the adjacent layer. A structure is shown with a layered channel having AlSb external layers and at least one or both of InAs and GaSb internal layers.

Abstract: A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-flop transistors. This results in a signal path with reduced series resistance and thus higher signals and a faster read operation obtainable. The density is additionally increased by using in common the primary injectors and the bit line injectors of adjacent cells of the array.

Abstract: A ballistic conduction majority carrier type semiconductor device structure can be fabricated with a built-in difference in barrier height between the emitter and collector interfaces by employing surface fermi level pinning in a crystalline structure with three copolanar regions of different semiconductor materials. The center region between the interfaces with the external zones of the structure has a thickness of the order of the mean free path of an electron. The materials of the external regions are such that there is a mismatch between the crystal spacing of the external regions and the central region which causes the fermi level of the material in the central zone to be pinned in the region of the conduction band at the interfaces with the external regions and the material of the external regions is selected so that the surface fermi level is pinned in the forbidden region. A monocrystalline structure having an emitter region of GaAs, a central or base region of InAs or W 100 .ANG. to 500 .ANG.

Abstract: Variable capacitance device consisting of a semiconductor substrate having a first conductivity type semiconductor layer, at least one second conductivity type semiconductor region formed in a surface portion of said first conductivity type semiconductor layer, and a barrier for generating a depletion layer formed on the surface opposite to said surface portion of said first conductivity type semiconductor layer, in which a capacitance reading-out section is disposed on said at least one second conductivity type semiconductor region.

Abstract: A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.

Abstract: Metallic contacts to compound semiconductor devices which employ a native oxide for passivation are provided. The metallic contacts of the invention comprise at least two metal layers: a first layer making non-rectifying contact with the semiconductor surface and providing a diffusion barrier and a second layer thereon comprising an easily oxidizable metal. A low resistivity metal layer may optionally be interposed between the two metal layers for improved conductivity.The metallic contact is formed prior to passivation. The diffusion barrier layer prevents diffusion of potentially deleterious materials into the semiconductor, while exposed portions of the oxidizable metal form an insulating oxide during anodic passivation in an electrolyte.

Abstract: A universal gate array is illustrated using a specific pattern of CMOS (Complementary Metal Oxide Silicon) Transistors in an array which provides a high degree of board utilization in the layout of small runs of integrated circuits where the high cost of completely customized boards is unacceptable. The array comprises a continuing pattern of two sets of three (3) series connected transistors in a cell surrounded on all four sides by cells each containing two single transistor gates of each channel type.

Abstract: A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.

Abstract: In a channel formed in one surface of a semiconductor substrate having a first conductivity, e.g. N type, a layer of material having a second conductivity type, e.g. P type boron, and a layer of relatively low resistance material such as Tungsten in contact with the first layer but insulated from the substrate. Second conductivity type tubs and the like can be formed adjacent the bus and in direct contact therewith through the first layer.

Abstract: A field effect transistor of the V-MOS type has a layer-shaped first region (3) of a first conductivity type, a subjacent second region (2, 1) of the second conductivity type and an island-shaped zone (4) of the second conductivity type. A V-shaped groove extends through the zone (4) and the first region (3) into the second region (2, 1) and is coated with an insulating layer (6) and a gate electrode layer (8). According to the invention, an insulating filler material (7) is present on the lower side of the groove (5) between the gate electrode (8) and the bottom of the groove (5) in order to increase the breakdown voltage.

Abstract: A self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polycrystalline silicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polycrystalline silicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal/polycrystalline silicon and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polycrystalline silicon is formed thereover.

Abstract: A first rectifying contact portion of a semiconductor device such as a Zener diode has a small area in order to attain a hard breakdown characteristic and a low noise characteristic. When a predetermined current which is not greater than the maximum allowable instantaneous value of non-D.C. currents flows through the first rectifying contact portion, a second rectifying contact portion which has a large area starts breakdown due to a voltage drop across a resistance component connected in series with the first rectifying contact portion and a breakdown voltage of the first rectifying contact portion.Owing to the fact that current is dispersed to the first rectifying contact portion and the second rectifying contact portion, a semiconductor device such as a Zener diode exhibiting a high endurance characteristic against surge voltages can be provided.

Abstract: A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.

Abstract: A stacked semiconductor IC device is disclosed which comprises a single-crystalline semiconductor substrate having planar surfaces with different height and a slant surface, a single-crystalline semiconductive layer which is epitaxially grown from the substrate on or above the substrate, and which has planar surfaces with different height and a slant surface and a substantially uniform thickness, groups of semiconductor elements each formed on the low planar surface of the substrate and on the low planar surface of the layer, and contact wiring pattern passing through the slant portion of the layer to electrically connect the element groups.