Abstract: An etching gas mixture containing CHF3, SF6 and a non-oxidizing gas such as Ar is used as an etching gas mixture for the anisotropic plasma-chemical dry-etching of a silicon nitride layer differentially or selectively relative to a silicon oxide layer. The gas mixture does not contain oxygen, chlorine, bromine, iodine or halides in addition to the above mentioned constituents, so that the process can be carried out in reactor systems equipped with oxidizable electrodes. By adjusting the gas flow rates or composition ratios of CHF3, SF6, and argon in the etching gas mixture, it is possible to adjust the resulting etching selectivity of silicon nitride relative to silicon oxide, and the particular edge slope angle of the etched edge of the remaining silicon nitride layer. A high etch rate for the silicon nitride is simultaneously achieved.

Abstract: Methods for the removal of anti-reflective layers during fabrication of integrated circuits are disclosed. In particular, an anti-reflective pattern or layer can be removed using a solution that includes a fluorine containing compound, an oxidant, and water. The fluorine containing compound in the solution can be hydrogen fluorine containing compound. Preferably, the oxidant in the solution is H2O2. The oxidant in the solution can also be ozone water. Related compositions are also disclosed.

Abstract: A plasma processing system and method wherein a power source produces a magnetic field and an electric field, and a window disposed between the power source and an interior of a plasma chamber couples the magnetic field into the plasma chamber thereby to couple power inductively into the chamber and based thereon produce a plasma in the plasma chamber. The window can be shaped and dimensioned to control an amount of power capacitively coupled to the plasma chamber by means of the electric field so that the amount of capacitively coupled power is selected in a range from zero to a predetermined amount. Also, a tuned antenna strap having r.f. power applied thereto to produce a standing wave therein can be arranged adjacent the window to couple magnetic field from a current maximum formed in the strap to the interior of the chamber.

Abstract: The present disclosure provides a method for etchback of a conductive layer in a contact via (contact hole). The method described is typically used in the formation of a conductive plug within the contact hole. The method includes a first etchback in which the conductive layer is etched back; a buffer (i.e., transition) step during which the etch rate of the conductive layer is reduced; and a second etchback in which the amount of chemically reactive etchant is reduced from that used in the first etchback and a plasma species is added to provide additional physical bombardment, in an isotropic etch of the substrate surface surrounding the contact hole.

Abstract: A wet etching system includes a tank for containing a chemical and having an open top portion, and a heater disposed in the tank for heating the chemical contained therein. A cover is arranged on the open top portion of the tank, and the cover includes a cooling apparatus formed therein. The wet etching method includes placing a semiconductor substrate, having a layer thereon to be etched, into the tank, and then driving the heater to maintain the chemical within a temperature range. Deionized water in the chemical evaporates when the temperature range is greater than a boiling point of the deionized water. The evaporated deionized water condenses on the cooler cover and then flows back into the tank to maintain a constant chemical concentration.

Abstract: A method for forming shallow trench isolation on a silicon wafer is described wherein a trench is formed using a silicon nitride/pad oxide hardmask having a silicon oxynitride ARC layer over the nitride. After a trench is formed by dry etching, the hardmask is recessed by first selectively recessing the silicon nitride and then exposing the upper corners of the silicon trench by wet etching the pad oxide thereby exposed. A first sacrificial oxidation converts a portion of the silicon oxynitride ARC layer to oxide and rounds off the sharp upper silicon corners of the trench. The sacrificial oxide is removed and a trench lining oxide is grown to a prescribed thickness by a second oxidation which converts the remaining silicon oxynitride into silicon oxide while further rounding the upper silicon trench corners. By converting the entire oxynitride ARC layer to oxide, it becomes possible to planarized the filler oxide into the silicon nitride layer with a CMP process having a high oxide-to-nitride selectivity.

Abstract: The invention describes a method for lowering particle count after tungsten etch back, in which method a plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.

Abstract: A method for removing sacrificial materials and metal contamination from silicon surfaces during the manufacturing of an integrated micromechanical device and a microelectronic device on a single chip is provided which includes the steps of adjusting the temperature of the chip using a reaction chamber to a temperature appropriate for the selection of a beta-diketone and the design of micromechanical and microelectronic devices, cycle purging the chamber using an inert gas to remove atmospheric gases and trace amounts of water, introducing HF and the beta-diketone as a reactive mixture into the reaction chamber which contains at least one substrate to be etched, flowing the reactive mixture over the substrate until the sacrificial materials and metal contamination have been substantially removed, stopping the flow of the reactive mixture; and cycle purging the chamber to remove residual reactive mixture and any remaining reaction by-products.

Abstract: An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for “zero” spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as “standard” logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability.

Abstract: A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip may then be performed by saw singulation or die punching.

Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.

Abstract: A slurry for polishing a metal film of a semiconductor device, comprising alumina-type fine particles having specific properties and composition, a polishing accelerator and water.

Abstract: A tank is set up to hold a precise volume of acid by first adjusting an overflow pipe to establish a volume that is larger than the desired volume and then adjusting the vertical position of a volume occupying element that extends above and below the surface of the acid. The apparatus includes a drain pipe for directing the acid to a tank that holds deionized water that the acid is mixed with. The bath is used for etching a silicon dioxide layer on a semiconductor wafer.

Abstract: A two-piece chuck for supporting a substrate in which a base plate allows the wafer to tilt and also exposes the underside of the wafer during wash/rinse cycle as well as during load/unload operations.

Abstract: An oxide etch process practiced in magnetically enhanced reactive ion etch (MERIE) plasma reactor. The etching gas includes approximately equal amounts of a hydrogen-free fluorocarbon, most preferably C4F6, and oxygen and a much larger amount of argon diluent gas. The magnetic field is preferably maintained above about 50 gauss and the pressure at 40 milliTorr or above with chamber residence times of less than 70 milliseconds. A two-step process may be used for etching holes with very high aspect ratios. In the second step, the magnetic filed and the oxygen flow are reduced. Other fluorocarbons may be substituted which have F/C ratios of less than 2 and more preferably no more than 1.6 or 1.5.

Abstract: A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.

Abstract: The present invention relates to a cleaning solution which can reliably remove the platinum group metal (e.g. Pt or Ir) contaminants adhering on the silicon-based insulating film (e.g. silicon oxide film) formed on a semiconductor substrate and further can prevent the readhesion of the removed contaminants, as well as to a cleaning method using said cleaning solution. Since the cleaning solution consists of HPFM or SPFM which is a mixture of a hydrochloric acid-hydrogen peroxide (HPM) or sulfuric acid-hydrogen peroxide (SPM) solution with a very small amount of hydrofluoric acid, the contaminants adhering on the silicon-based insulating film can be reduced to a level lower than 1×1010 atoms/cm2.