Abstract: A combination CMP-etch method for forming a thin planar layer over the surface of a device includes the steps of providing a substrate including a plurality of surface projections defining gaps therebetween, forming an etchable layer on the substrate, performing a CMP process on the etchable layer to form a planar layer having a first thickness in excess of 1,000 Angstroms, and etching the planar layer to a second thickness less than 1,000 Angstroms. In a particular method, the step of forming the etchable layer includes the steps of forming an etch resistant layer on the substrate, forming a fill layer on the etch-resistant layer, etching the fill layer to expose portions of the etch-resistant layer overlying the projections, and to leave a portion of the fill layer in the gaps, and forming the etchable layer on the exposed portions of the etch-resistant layer and the fill layer.

Abstract: An XeF2 source includes a XeF2 source chamber having a tray or ampoule for XeF2 crystals, a reservoir coupled to the XeF2 source chamber via a valve, a flow controller fed by the reservoir and a valve between the reservoir and the flow controller. Pressure sources are provided respectively to maintain the reservoir and the source chamber at the sublimation pressure of XeF2. The arrangement allows for a steady supply of XeF2 to an etching chamber.

Abstract: A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.

Abstract: The present invention provides a processing method of outermost periphery edge part of silicon wafer comprising, etching the outermost periphery edge of silicon wafer by activated species gas generated in plasma. The plasma activated species gas can be generated by dissociation of, for example, sulfur hexafluoride gas in a discharge tube 8. Further, provides a processing apparatus for etching of outermost periphery edge of silicon wafer by means of plasma etching method comprising, a means to hold and rotate a silicon wafer 1, a container 5 which covers all surface of silicon wafer except a part of outermost periphery edge, a vacuum chamber 10 which contain said container and a plasma generating means 11.

Abstract: A fabrication process of a semiconductor device with a titanium film includes the steps of forming a titanium film on a substrate by way of a chemical vapor deposition method; and removing titanium deposited within a reaction chamber forming the titanium film by a gas containing halogen, following the titanium film forming step.

Abstract: Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical planarizing processes. In one aspect of the invention, a microelectronic-device substrate assembly is planarized by abrading material from the substrate assembly using a plurality of first abrasive particles and removing material from the substrate assembly using a plurality second abrasive particles. The first abrasive particles have a first planarizing attribute, and the second abrasive particles have a second planarizing attribute. The first and second planarizing attributes are different from one another to preferably selectively remove topographical features from substrate assembly and/or selectively remove different types of material at the substrate surface.

Abstract: A wet etching system includes a tank for containing a chemical and having an open top portion, and a heater disposed in the tank for heating the chemical contained therein. A cover is arranged on the open top portion of the tank, and the cover includes a cooling apparatus formed therein. The wet etching method includes placing a semiconductor substrate, having a layer thereon to be etched, into the tank, and then driving the heater to maintain the chemical within a temperature range. Deionized water in the chemical evaporates when the temperature range is greater than a boiling point of the deionized water. The evaporated deionized water condenses on the cooler cover and then flows back into the tank to maintain a constant chemical concentration.

Abstract: Disclosed is a method for fabricating an electrode of a plasma chamber. According to the method, a circular silicon substrate is provided facing a drilling plate having a plurality of tips projected from one surface of the drilling plate. Afterwards, a polishing material containing a plurality of polishing particles is supplied on the circular silicon substrate and the drilling plate. Thereafter, an ultrasonic wave is applied to the drilling plate to vibrate the tips of the drilling plate. The plurality of polishing particles collide with the circular silicon plate during the vibration of the tips of the drilling plate and a plurality of fine through holes are thereby formed in the circular silicon plate.

Abstract: An etching method and an etching apparatus are provided. Silicon (Si) from surfaces semiconductor wafers W dissolves into an etching liquid E stored in a process bath 10. On detection of the concentration of silicon by a concentration sensor 50, the etching liquid E in the process bath 10 is discharged while leaving a part of the etching liquid when the Si concentration in the etching liquid E reaches a designated concentration. After that, a new etching liquid of substantially equal to an amount of the discharged etching liquid E is supplied into the process bath 10 and added to the etching liquid remaining in the bath 10. Consequently, it is possible to restrict the etching rate just after the exchange of etching liquid from rising excessively.

Abstract: An apparatus, as well as a method, brings a surface of a substrate into contact with a polishing pad that has a window, causes relative motion between the substrate and the polishing pad, and directs a light beam through the window so that the motion of the polishing pad relative to the substrate causes the light beam to move in a path across the substrate. An extreme intensity measurement is derived from a plurality of intensity measurements made as the light beam moves across the substrate. The beam sweeps across the substrate a plurality of times to generate a plurality of extreme intensity measurements, and a polishing endpoint is detected based on the plurality of extreme intensity measurements.

Abstract: A method of planarizing an oxide layer. The method includes performing an isotropic chemical dry etching operation using a nitrogenous processing gas. Furthermore, oxygen can also be added to the nitrogenous processing gas during the isotropic chemical dry etching operation. In addition, the nitrogenous processing gas can be nitrogen or a nitrogen-oxygen compound, where the nitrogen-oxygen compound can be nitrogen monoxide, nitrogen dioxide or nitrous oxide.

Abstract: A method of producing a pump body having an inlet opening provided with an inlet valve (106) and an outlet opening provided with an outlet valve (108), said method comprising as a first step the step of structuring a respective first main surface of a first and of a second semiconductor disc (200) for defining a valve flap structure (202) of the inlet valve and a valve seat structure (204) of the outlet valve in the first disc and a valve flap structure of the outlet valve and a valve seat structure of the inlet valve in the second disc. Following this, a valve flap well structure (206; 216) and a valve opening well structure (208; 218) are formed in a predetermined relationship with the valve flap structures and the valve seat structures in a respective second main surface of the first and of the second semiconductor disc.

Abstract: The present invention relates to a method for fabricating an inductor and, more particularly, to a method for fabricating a spiral inductor used in a monolithic microwave integrated circuit on a silicon substrate using semiconductor fabrication processes. The method for fabricating an inductor, comprising the steps of: forming a first dielectric layer on a silicon substrate and forming a first metal wire on the first dielectric layer, wherein the first metal wire is in contact with an active element formed on the silicon substrate; and alternatively forming dielectric layers and metal layers, wherein the metal layers are electrically connected with an upper metal wire and a lower metal wire and wherein the metal layers are patterned using the dielectric layers as etching mask, whereby a metal corrosion is prevented by using the spiral dielectric pattern as the etching mask.

Abstract: A waferless seasoning process is described, which waferless seasoning process is suitable for an etching chamber of an etching machine when the etching environment is so bad that etching cannot be performed. A dry cleaning process with a plasma formed by oxygen and hydrogen bromide is performed to restore the etching environment in the etching chamber.

Abstract: A first layer of InP is deposited on a diffraction grating so as to cover it, by MOCVD in which PH3 or organophosphorus is used as a source material of P and in which H2 is used as a carrier gas. The substrate is heated up to a temperature which is higher than the substrate temperature during the first layer deposition, and then a second layer is deposited on the first layer. An active layer is deposited on the second layer. Found out is such a growth rate of an InP layer as to cause the photoluminescence intensity of a layer corresponding to the active layer to be one tenth as small as that when the InP layer is deposited at a growth rate of 0.

Abstract: A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step.

Abstract: A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method.

Abstract: A precision polishing method and a precision polishing apparatus are adapted to be used with a chemical etching technique of utilizing a chemical effect for polishing a metal film without producing any process-altered layer nor any scratches on the metal surface and without the risk of partly burying the polishing agent near the metal surface in order to flatten and smooth or remove the metal film. With a precision polishing method and a precision polishing apparatus according to the invention, the surface to be polished of a substrate 1 carrying thereon a metal film for forming a semiconductor device is pressed against a hard polishing pad 4, while an etching solution 7 is supplyed to the surface to be polished and that of the polishing pad 4 that are held in contact with each other and the surface to be polished and the polishing pad 4 are driven to move relative to each other.

Abstract: Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.

Abstract: Described is a process for using chemical-mechanical planarization in the manufacture of Damascene structures that substantially reduces unwanted topography. The process is implemented in two stages to separate bulk metal removal and interface clearing. In stage 1 a top metal layer is planarized both globally and locally by CMP removal at a high rate of the preponderance of overlying metal, without penetrating to dielectric or barrier materials and with a minimum of CMP-generated global topography. For stage 2, the slurry is formulated with a 1:1:1 removal rate selectivity as to the metal/barrier/dielectric materials, the object being to preserve the highly flat topography achieved in stage 1.