Abstract: A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics.

Abstract: A system and associated method for generating a Service Component Architecture (SCA) module with Service Oriented Architecture (SOA) model elements. A service model is created according to a process model that has activities and a process flow. Services of the service model are respectively associated with the activities. Each service is determined to employ only one service operation definition to render a message specification of a respective activity that is associated with each service. The activities, the process flow, and the message specification are utilized to produce the SCA module in executable implementations.

Abstract: There is described a method for determining the processing sequence of components of a function plan for a sequentially operating automation system. Each component is allocated a component code in a reversible unambiguous manner and, while the components have a signal input and output connection, these should be applicable to a number of various function plans and thus minimize the reaction time of an automation system to process signals. The above is achieved, whereby the signal path in the function plan commences at an initial component in a recursive procedure in the forward direction and returns in the backward direction.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A code generation system is optimized by integrating input data. An input code to the code generation system has a program code and an annotation. The program code is a program text to be automated by the code generation system. The annotation has code generating instructions to process the program code. An input code parser generates a template that parameterizes texts of the program code for automatically generating an output code. The input code parser produces a model to instantiate parameterized program code for each parameter. The template is used as inputs to a template engine of the code generation system and produces a code generator. An output code is created by applying the model to the code generator.

Abstract: Techniques for authenticating one or more configuration items in an information repository are provided comprising the step of running an audit on the one or more configuration items in accordance with a change history of each of the one or more configuration items and one or more request for change identifiers.

Abstract: Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.

Abstract: A system, method, and computer program product are provided for hooking code inserted into an address space of a new process. In use, creation of a process is identified. Additionally, code is inserted into an address space of the process. Still yet, at least one module being loaded in association with the process is identified. Further, the code is hooked at an entry point of the at least one module based on a determination of whether the at least one module includes a predefined module.

Abstract: An apparatus and method for initializing system global variables by using a multiple load/store instruction is disclosed. The apparatus includes: a first storing unit for storing a system global variable initialization function and initialization functions using multiple load/store instruction; a second storing unit for storing a return address; a control unit for storing a first return address to the second storing unit when the system global variable initialization function is called for initializing the system global variable, initializing the system global variables by calling the initialization functions using multiple load/store instruction while performing the system global variable function and performing a rest of system global variable initialization function by finding and executing an execution sequence based on the first return address stored in the second storing unit; and a third storing unit for storing the system global variables initialized according to the control unit.

Abstract: Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.

Abstract: There is provided an autonomic software system and method for normalizing a profile collected for an executing application to account for one or more actions applied to the executing application after the profile was collected, comprising: predicting an impact of applying the one or more actions to the executing application by utilizing the profile and the one or more actions; and adjusting the profile to form a normalized profile according to the predicted impact. A plurality of different a profile consumers, such as, a phase shift detector, an action evaluator as well as a normalizing controller, may utilize the normalized profile to improve the behavior of the executing application. In addition, online visualization tools may be implemented to graphically depict the normalized profiles, as well as differences between the collected profiles and the normalized profiles.

Abstract: A read channel of a magnetic data storage device includes a filter to provide equalization of the signal being detected from the magnetic media. The filter utilizes coefficients for the filter response. The filter coefficients may drift sideways over time. The drift is detected and a correction is implemented by imposing a leakage on the coefficients to re-center the filter response. The leakage sign differs depending on the direction of drift detected.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating a computer program. A system configured to practice the method identifies a set of executable instructions at a first location in an instruction section of the computer program and identifies a second location in a data section of the computer program. Then the system moves the set of executable instructions to the second location and patches references in the computer program to the set of executable instructions to point to the second location. The instruction section of the computer program can be labeled as _TEXT,_text and the data section of the computer program is labeled as _DATA,_data. The set of executable instructions can include one or more non-branching instructions optionally followed by a branching instruction. The placement of the first and second locations can be based on features of a target computing architecture, such as cache size.

Abstract: We describe a method for using a classical computer to generate a sequence of elementary operations (SEO) that can be used to operate a quantum computer. A quantum computer operating under such a SEO can be used to evaluate certain quantum operator averages.

Abstract: Embodiments include a system for loading components with complex intra-dependencies. Components in the system may be assigned at start up to a common loader module. The system detects reference cycles amongst the set of components in the system. All components in a reference cycle may be assigned for loading to the same common loader. This system avoids deadlock scenarios by identifying reference cycles at start up and assigning each cycle to a single common loader. The embodiments of the system also analyze components to be loaded that are identified after start up to determine if they cause a new reference cycle. Components that cause a new reference cycle may not be allowed to be loaded to prevent deadlock loading scenarios.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

Abstract: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.

Abstract: A down conversion filter with a plurality of sampling capacitor, wherein at least one sampling capacitor is discharged in sampling phases or charge-summing phases of the other sampling capacitors.

Abstract: A method that may include: monitoring over time, actions carried out by at least one programmer over a software development environment to yield development patterns; comparing the development patterns to best practice rules to yield a comparison results indicating deviations of the development patterns from the best practice rules; and analyzing the comparison results based at least partially on a likelihood of each action deviated from the respective best practice rule to result in a software bug, to yield an analysis of potential software bug prone code sections, wherein at least one of the monitoring, the comparing, and the analyzing is executed by at least one processor.