Abstract: A method for manufacturing a waveguide-type semiconductor device includes the steps of forming an epitaxial structure including a waveguide mesa and a device mesa; forming a mask for selective growth on the epitaxial structure; growing a semiconductor region on an end surface of the device mesa by using the mask for selective growth, the semiconductor region including a side portion having a layer shape and a protruding wall portion; forming an ohmic electrode on a top surface of the device mesa; forming a resin layer on the device mesa and the semiconductor region; forming a resin mask having an opening on the ohmic electrode; forming an electric conductor connecting the ohmic electrode to an electrode pad, the electric conductor passing over the protruding wall portion while making contact with a surface of the resin mask; and removing the resin mask after forming the electric conductor.

Abstract: A display panel device includes: a gate electrode above a substrate; a gate insulator above the gate electrode; a first source electrode and a first drain electrode above the gate insulator; a second source electrode and a second drain electrode above the first source electrode and the first drain electrode respectively; a first partition wall part having an opening in which the second source electrode and the second drain electrode are exposed; a semiconductor layer in the opening; an insulation layer above the semiconductor layer; a lower electrode above the insulation layer; and a contact hole in the insulation layer, for connecting the lower electrode and the second drain electrode or the second source electrode, wherein a film structure of each of the second source electrode and the second drain electrode is sparser than a film structure of each of the first source electrode and the first drain electrode.

Abstract: A method of fabricating an organic electroluminescence display device includes providing a substrate including a plurality of pixel regions, first electrodes, and a partition wall, the pixel regions including two pixel columns, providing a mask including openings and first inclined surfaces, the openings being at positions corresponding to the two pixel columns, each of the first inclined surfaces being inclined toward one of the openings and including a portion extending to a region between the two pixel columns, positioning the mask such that each of the openings faces a portion of one of the pixel regions, dropping a solution containing an organic electroluminescence material onto the first inclined surfaces such that the solution is supplied onto the first electrodes through the openings to coat the first electrodes, evaporating solvent from the solution to form an organic electroluminescence layer, and forming a second electrode on the organic electroluminescence layer.

Abstract: An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure.

Abstract: A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.

Abstract: An organic EL element comprises: an anode; a cathode; a buffer layer; and a hole injection layer between the anode and the buffer layer. The hole injection layer includes a nickel oxide that includes both nickel atoms with a valence of three and nickel atoms with a valence of two. At least part of the hole injection layer has a crystal structure AaNibOc that includes nickel, a metal element A, and oxygen, the nickel including nickel atoms with a valence of three, and the metal element A differing from nickel and including metal A atoms with a valence of three.

Abstract: The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion.

Abstract: A mother substrate for an organic light-emitting display apparatus. The mother substrate has a panel area and a peripheral area surrounding the panel area, pixels disposed in a display area of the panel area, pads that are disposed in a non-display area of the panel area and are coupled to the pixels, test wirings disposed in the peripheral area, a local buffer electrically connected to the test wirings, a bridge wiring connecting the local buffer to one of the pads, and a dummy resistance layer having one end in contact with the bridge wiring and another end in contact with one of the test wirings.