Abstract: A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.

Abstract: In conventional unified storage systems, an I/O for block storage and an I/O for file storage are processed in a single OS without being distinguished, so that it was not possible to perform processes for speedy failure detection or for enhancing performances such as tuning of performance by directly monitoring hardware. The present invention solves the problem by having a block storage-side OS and an OS group managing multiple systems including a file system other than the block storage-side OS coexist within a storage system, wherein the OS group managing multiple systems including a file system other than the block storage-side OS is virtualized by a hypervisor, wherein a block storage micro-controller and the hypervisor can cooperate in performing processes.

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract: A network attached storage (NAS) caching appliance, system, and associated method of operation for caching a networked file system. Still further, some embodiments provide for a cache system that implements a mufti-tiered, policy-influenced block replacement algorithm.

Abstract: A mechanism is provided in a data processing system for asynchronous replication. The mechanism creates a record in a write log in a host computing device for a write command and marking the record as uncommitted. The mechanism maintains a copy of data to be written by the write command at the host computing device. The mechanism issues the write command from the host computing device to a primary storage controller at the primary storage site. Responsive to receiving an acknowledgement from the primary storage controller that the data have been written to the primary storage site, the mechanism marks the record as unreplicated. Responsive to receiving an acknowledgement from the primary storage controller that the data have been replicated to a secondary storage site, the mechanism erases the record in the write log and deleting the copy of data.

Abstract: To facilitate both minimal allocations and adaptive allocations, two sets of storage group policies are defined—one policy setting minimal allocation values for storage group access to storage resources and one policy setting maximal allocation values for storage group access to storage. In addition, a set of priority weights is specified that is used to balance access to storage tiers across storage groups. Upon existence of contention for storage resources, minimum allocation values for storage groups are determined based on the priority weights for the storage groups, resulting in threshold values being set to enable at least partial access to storage resources for all storage groups without requiring priority weighting of the activity density distributions of the competing storage groups. Allocations other than the minimal allocations are provided based on relative activity density distribution of storage extents between groups.

Abstract: Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Abstract: A method for detecting patterns of memory accesses in a computing system with out-of-order program execution is provided. The method comprises identifying a first memory operation instruction that is part of a memory stream that would benefit from memory prefetches, marking with program order a plurality of other memory operation instructions prior to execution that are part of the same memory stream as the first memory operation instruction while the plurality of other memory operation instructions are in program order, and, subsequent to out of program order execution of at least two of the plurality of marked memory operation instructions but before execution of all of the plurality of marked memory operation instructions, determining an expected offset value between memory addresses to be accessed by consecutively marked memory operation instructions using the marked memory operation instructions that have executed.

Abstract: Technologies are described herein for providing a hardware-based accelerator adapted to manage copy-on-write. Some example technologies may identify a read request adapted to read a block at an original memory address. The technologies may utilize the hardware-based accelerator to determine whether the block is located at the original memory address. When a determination is made that the block is located in at the original memory address, the technologies may utilize the hardware-based accelerator to pass the original memory address so that the read request can be performed utilizing the original memory address. When a determination is made that the block is not located in the memory at the original memory address, the technologies may utilize the hardware-based accelerator to generate a new memory address and to pass the new memory address so that the read request can be performed utilizing the new memory address.

Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.

Abstract: Techniques are disclosed for reducing perceived read latency. Upon receiving a read request with a scatter-gather array from a guest operating system running on a virtual machine (VM), an early read return virtualization (ERRV) component of a virtual machine monitor fills the scatter-gather array with data from a cache and data retrieved via input-output requests (IOs) to media. The ERRV component is configured to return the read request before all IOs have completed based on a predefined policy. Prior to returning the read, the ERRV component may unmap unfilled pages of the scatter-gather array until data for the unmapped pages becomes available when IOs to the external media complete. Later accesses to unmapped pages will generate page faults, which are handled by stunning the VMs from which the access requests originated until, e.g., all elements of the SG array are filled and all pages of the SG array are mapped.

Abstract: An improved technique for a data storage apparatus that combines both block-based and file-based functionality in a unified data path architecture. The improved technique brings together IO processing of block-based storage systems and file-based storage systems by expressing both block-based objects (e.g., LUNs) and file-based objects (e.g., file systems) in the form of files. These files are parts of an underlying, internal set of file systems, which are stored on a set of storage units served by a storage pool. Because block and file-based objects are all expressed as files of this set of file systems, a common set of services can be applied across block-based and file-based objects. Also, storage units released by any file or files of the underlying, internal set of file systems can be reused by any other file or files, regardless of whether the files represent block-based objects or file-based objects. Inefficiencies of stranded storage are thus greatly reduced or eliminated altogether.

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: An exact match lookup system includes a hash function that generates a hash value in response to an input hash key. The hash value is used to retrieve a hash bucket index value from a hash bucket index table. The hash bucket index value is used to retrieve a plurality of hash keys from a plurality of hash bucket tables, in parallel. The retrieved hash keys are compared with the input hash key to identify a match. Hit logic generates an output index by concatenating the hash bucket index value with an address associated with the hash bucket table that provides the matching hash key. An exact match result is provided in response to the output index. A content addressable memory (CAM) may store hash keys that do not fit in the hash bucket tables.

Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.