Abstract: An I/O hint framework is provided. In one embodiment, a computer system can receive an I/O command originating from a virtual machine (VM), where the I/O command identifies a data block of a virtual disk. The computer system can further extract hint metadata from the I/O command, where the hint metadata includes one or more characteristics of the data block that are relevant for determining how to cache the data block in a flash storage-based cache. The computer system can then make the hint metadata available to a caching module configured to manage the flash storage-based cache.

Abstract: Techniques for evicting cached files may be realized as a method including: maintaining a file system cache storing selected files from a file storage; for files that are above a threshold size, selectively storing chunks of the files; for each file that is stored, associating an access bit and a size bit with that file; for each file that is stored selectively as file chunks, associating an access bitmap to the file having an access bit associated with each file chunk; when a file is accessed, setting the access bit associated with the file and file chunk to indicate recent access; at set intervals, periodically clearing the access bits to not indicate recent access; and carrying out a cache eviction process comprising evicting at least one file or file chunk associated with an access bit that does not indicate recent access.

Abstract: A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Abstract: A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value.

Abstract: Examples disclose partitioning a volatile memory into a high performance partition and a low performance partition. Further the example discloses retrieving an application with a high performance data and a low performance data from a non-volatile memory to place the high and the low performance data in the high and low performance partitions, respectively. Additionally, the example also discloses receiving a request to decrease power and in response, reduce an amount of power to the high performance partition and maintaining an amount of power provided to the low performance partition.

Abstract: A multiport memory having an array of storage cells for storing data; a plurality of data access ports; and access control circuitry to assign each data access port to one of the sets of access control lines and corresponding data lines. The control circuitry has collision detection circuitry to detect a colliding data access request received at a second data access port that requests access to a row of storage cells currently being accessed by a data access request received at a first data access port. The control circuitry is responsive to the detected collision to assign the set of access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and to subsequently assign the first data access port to the set of access control lines and corresponding data lines previously assigned to the second access port.

Abstract: A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.

Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

Abstract: A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.

Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.

Abstract: An I/O request to store a file in a file-system is received. A determination is made whether the size of the file does not exceed a threshold size. Exceeding the threshold results in storing at least a portion of the file in a block of the file-system devoid of sub-blocks. A determination is made whether the size of the file does not exceed a size of unallocated space within a single block in the file-system. The single block includes a set of sub-blocks. Responsive to the size of the file not exceeding the threshold size and the size of unallocated space within the single block, the file is stored, at an address, in a first subset of the set of the sub-blocks of the single block. The address identifies the single block and a position of a sub-block in the subset.

Abstract: Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Abstract: A system that implements a scalable data storage service may maintain tables in a data store on behalf of storage service clients. The service may maintain table data in multiple replicas of partitions that are stored on respective computing nodes in the system. In response to detecting an anomaly in the system, detecting a change in data volume on a partition or service request traffic directed to a partition, or receiving a service request from a client to split a partition, the data storage service may create additional copies of a partition replica using a physical copy mechanism. The data storage service may issue a split command defined in an API for the data store to divide the original and additional replicas into multiple replica groups, and to configure each replica group to maintain a respective portion of the table data that was stored in the partition before the split.

Abstract: Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.

Abstract: Dynamically creating a communication path between first and second storage devices, includes creating a connection to a source volume on the first storage device and indicating that the source volume is not ready to transmit data on the communication path, after successfully creating the connection to the source volume, creating a connection to a destination volume on the second storage device and initially indicating that portions of one of: the destination volume and the source volume do not contain valid copies of data, where the destination volume accepts data from the source volume, and after successfully creating the connections to the source and destination volumes, indicating that the source volume is ready to transmit data on the communication path. Dynamically creating a communication path between first and second storage devices, may also include creating at least one of: the source volume and the destination volume.

Abstract: A method for data migration between storage devices according to an embodiment of the invention comprises: collecting an original time domain sequence of workload parameters of a data volume in a low speed storage device; evaluating a workload period of the data volume based on the collected original time domain sequence of the workload parameters; and migrating the data in the data volume according to the evaluated workload period so that the data is located in a high speed storage device during a workload peak of the data volume. The embodiments of the invention can improve a data access speed in the storage devices.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.