Abstract: A portable compact device for use with an external device. The portable compact device includes an interface circuit for providing an interface between an external device and the portable compact device. A data memory circuit stores data received by the interface circuit. A control circuit coupled to the data memory circuit processes data stored in the data memory circuit in accordance with a stored data structure. A data modifying circuit is coupled to the data memory circuit for modifying the stored data. A data structure initializing circuit insures that the structure of the stored data in the data memory circuit allows the control circuit to process the stored data.

Abstract: A computer memory system for use with a user processor provides automatic memory operations independently of the user processor. The memory system includes a logical memory system which is accessed by the user processor through a binding register unit, enabling the user processor to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The user cannot access the memory directly, but must access the memory through the binding registers. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the user processor.

Abstract: An apparatus for incorporation in each memory-using component of a data processing system permits locking of a portion of the memory, which portion may be as small as a single location, for atomic read-modify-write operations while permitting unlimited access to the memory for read operations and access to all but the locked portion for non-atomic write operations.

Abstract: In a communication and control system, an improved interface between a digital IC and its associated microcomputer is provided wherein a serial shift register in the digital IC is used to store the message bits of a received message and control of the shift register is transferred to the associated microcomputer as soon as the interface is set up so that data stored in the register is not overwritten by another received message. A busy signal is also supplied over one line of the interface only during periods when the digital IC is actually receiving or transmitting a message.

Abstract: A computerized information retriveal system is formed of a textbase of texts of variable length and content. The texts are selected from the textbase on the basis of Boolean logic searches among keywords associated with the texts. When a group is retrieved from such a search, the system automatically segregates the texts based on the presence or absence of a criterion key keyword selected so as to segregate the texts into sub-groups. The same criterion key analysis can then be applied recursively to the sub-groups. The resulting sub-groups are then displayed to the user in a hierarchical display to illustrate the relationships amoung the texts. A string comparison routine is also disclosed to search for similar keywords.

Abstract: A digital data processor of the type having a plurality of data inputs and a plurality of data latches, each coupled to one of said data inputs is modified to accomodate pattern driven interrupt. A plurality of bit comparators, each having inputs coupled to one of the said data inputs and one of said data latches, compare the input pattern to a stored pattern. The outputs of the bit comparators are ANDed to indicate one of a match and a mis-match between the two patterns. Interrupt generation logic is selectable to generate an interrupt request on one of the match and mis-match indications. The apparatus and method are particularly suited to use in a microcontroller which requires fast and software-efficient pattern driven interrupt.

Abstract: In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Abstract: To detect a memory protection violation at high speed in a data processor for executing microinstructions, plural memory protection information of a descriptor of a new segment program are simultaneously discriminated true or false on the basis of current privilege level and branch condition information of a memory protection branch microinstruction. If discriminated true, the succeeding microinstruction is selected. If false, the current microinstruction is branched to a designated branch address included in the branch microinstruction. The apparatus comprises, an attribute information register for storing plural memory protection information of a new decriptor; a current privilege level register; a privilege level comparator; a microinstruction register for storing a memory protection branch microinstruction including plural branch condition information and a branch address; a memory protection violation detector having AND gates, inverters, and an OR gate; and a read address selector having an adder, etc.

Abstract: A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit.

Abstract: Methods and apparatus are set forth for optimizing the performance of instruction processors using an instruction cache memory in combination with a sequential transfer main memory. According to the invention, the memory system stores preselected instructions in cache memory. The instructions are those that immediately follow a branch operation. The purpose of storing these instructions is to minimize, and if possible, eliminate the delay associated with fetching the same sequence from main memory following a subsequent branch to the same instruction string. The number of instructions that need to be cached (placed in cache memory) is a function of the access time for the first and subsequent fetches from sequential main memory, the speed of the cache memory, and instruction execution time. The invention is particularly well suited for use in computer systems having RISC architectures with fixed instruction lengths.

Abstract: A program skip operation control system used in a prefetched processor includes at least a program memory for storing a number of instructions, an instruction register associated to the program memory to fetch an instruction to be executed, and an instruction decoder receiving the content of the instruction register so as to generate a decoded instruction. An instruction address register is associated to the program memory to updateably prefetch an address of an instruction to be next fetched from the program memory to the instruction register, so that in the course of execution of the decoded instruction outputted from the instruction decoder, an instruction to be next executed is fetched from the program memory to the instruction register. The instruction decoder responds to a skip signal so as to invalidate the decoded instruction and generate a no-operation instruction for at least one cycle after a predetermined skip operation has been carried out.

Abstract: A transmitter couples an output to a loop which represents a sensed process variable such as pressure. A microprocessor-based circuit in the transmitter senses the process variable and computes an output signal and provides the output to the loop. A communication circuit in the transmitter receives a high frequency signal including a transmitter parameter from the loop. The communication circuit couples the parameter to the microprocessor. The microprocessor couples the parameter to an EEPROM. The high energization requirements of the EEPROM during a WRITE interval are supplied by an energization circuit. The energization circuit receives energization from the loop at a low rate so that the output is not substantially disturbed. The energization circuit stores energy and supplies energization to the EEPROM during the WRITE time interval without substantially disturbing the loop current.

Abstract: To perform a binder through retrieval on binders which are set out on an optical disk and have different title structures, those binders containing the same key attribute data as a designated retrieval key are retrieved. When binders to be linked are selected from the retrieved binders, only those keys containing the same attribute data as the designated key are extracted from the selected binders. The extracted keys are sequentially arranged in the extracted order, thereby creating a title table for a link binder on a magnetic disk. This title table is retrieved to provide desired image imformation. Alternatively, a binder number/key correlation table is created on the magnetic disk, in accordance with the selection of the binders to be linked. This binder number/key correlation table includes the quantity of linked binders, the number of retrieval keys, the number of each binder and information relating to linked keys for each one of the linked binders.

Abstract: An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.

Abstract: A tunable operating system in a multiprogrammed data processing system provides improved throughput of tasks blocking on inter-task message requests before time-slice runout. A ready queue subset is defined for each task; the queue subsets for different tasks are overlapped by at least one queue. Dispatch priority is improved when a task requests inter-task message service before time-slice runout, and worsened when a task runs out the time slice. The task is dispatched from a queue in its subset corresponding to the dispatch priority. One of a plurality of time-slice values is assigned when a task is dispatched; the time-slice values are assigned with respect to the position of the task within its queue subset and therefore are not fixed with respect to each queue. The operating system sets the timer to await completion of a full time slice upon each dispatch.

Abstract: In a computer system suitable for effecting a sequence control and a servo-control, programs are prepared by using three types of parallel processing instructions consisting of an open instruction, a close instruction is issued from a first program for parallelly processing a second program. The close instruction is issued from the first program to terminate the first or second program. The pause instruction is issued from the first program to stop execution of the first program for a definite interval.

Abstract: Operation of a microcomputer-based instrument is controlled by software including a control interface system, a command execution system, and a steady state system. The steady state system includes a group of subsystems operating as concurrent tasks, each carrying out various instrument operations. The control interface system includes a set of subsystems, each responsive to configuration control input signals from a separate control signal source, and each converting configuration control signals into "configuration commands". Each command identifies a particular procedure for configuring the operating state of one or more instrument hardware or software steady state subsystems of the instrument. Each command is stored in memory in one of several queues (one for each control interface subsystem) until the procedure it invokes is carried out.

Abstract: A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").

Abstract: A vector file organization for a multiple pipelined vector processor with data transfer capability to support multiple program execution pipelines. Multiple pipelines can simultaneously access various blocks of the vector file through segmenting the file storage and by addressing the various elements of the segments. Vector files of programmable registers each have storage for sixty-four elements of 36-bit words or thirty-two elements of 64-bit words. Six independent execution pipelines in combination can programmably access the vector files for either read operands or write operands or both. Each vector file has N independent blocks, each using a RAM with read output to the pipelines, an address register and a write data register. Each block holds interspersed word pairs of words of each vector file. Primary and secondary vector files are equal in capability and allow reading pairs of elements, as required by arithmetic instructions.