Abstract: A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands.

Abstract: An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry.

Abstract: A method of operating a computer system to effect user-customization, primarily foreign language translation, of standard system-supplied screen displays without the need to modify underlying system source code. A transltion environment includes an autonomous processor (250) interposed between a host system (100) and access devices (201,202). Information transmitted between the host and access device is diverted to the processor for intermediate processing. One phase of this processing generates a translation file (500) which stores a mapping relationship between a first language screen and its second language counterpart. This translation file is invoked during the secod processing phase to effect a translation from the first-to-second language upon a host response and from the second-to-first language upon a host request.

Abstract: This invention relates generally to techniques for designing electrical circuitry and more specifically relates to a method for determining the minimum number of storage elements required to store the states of circuit. This determination is achieved by combining the output states of a circuit which occur during a pair of adjacent clock intervals into a combined state occurring during a combined clock interval. The combining step is then repeated until all possible ones of the combined states have been obtained. Still more specifically, the method includes the step of generating, prior to the combining step, a waveform pattern showing the output states of the circuit. Once the minimum number of combined states is determined, the minimum number of storage elements required can be determined by invoking the equation: m= log.sub.2 n , wherein m is the number of storage elements or memory registers and n is the sum of all possible ones of the combined states.

Abstract: Data are asynchronously transferred between a microprocessor and a dynamic memory under the control of a memory controller and a circuit for deriving an internal acknowledgment signal. The internal acknowledgment signal is derived in response to the memory controller deriving a signal indicating that the memory is unavailable at the time a transfer request is derived by the microprocessor or in response to a transfer request derived by the microprocessor. A mask signal is generated in response to the transfer request, a clock signal and a previously derived value for the mask signal. The mask signal has a duration to guarantee a minimum data transfer time between the memory and the microprocessor compatible with the access time T of the memory. The mask signal is combined with the internal acknowledgment signal to control the microprocessor supplying signals to the memory.

Abstract: An apparatus controls the movement of a data block between a peripheral and a data processing system, which comprises a bus which includes an address bus, a first data bus, and a second data bus, the peripheral being connected to the second data bus. A first memory, connected to the second data bus, stores data, and a second memory, connected to the first data bus, stores a plurality of dummy routines in predetermined areas, the predetermined areas of the second memory having corresponding buffer areas in the first memory. The first memory and the second memory correspond to a first memory area and a second memory area within a total predefined memory space, each memory location within the total memory space being defined by a unique memory space address. A processor connected to the first data bus, fetches an instruction, in response to a control signal from the peripheral, from a preselected one of the dummy routines.

Abstract: A data processing unit with a TLB purge function has an address counter in which TLB purge data including an address space identifier, segment number, and page number are held. In TLB purge processing, A TLB is indexed by the upper data from the counter so that for the contents of the corresponding entry, an upper address space identifier, an upper segment number, an upper page number, and a valid flag are connected to a TLB hit detector. The lower data from the counter and three mask bits of a nano-instruction are also connected to the TLB hit detector. The TLB hit detector includes three comparators which compare the upper address space identifiers, the upper segment numbers, and the upper page numbers, which are respectively derived from the counter and the TLB. The result of each comparison and a mask bit are ORed. The ORed signal and the valid flag are supplied to an AND gate, thereby checking whether the TLB hit is present or not.

Abstract: A software performance analyzer nonintrusively measures six different aspects of software execution. These include histograms or a table indicating the degree of memory activity within a collection of specified address ranges, or indicating the amount of memory of bus activity caused by the execution of programming fetched from within a collection of specified ranges, or indicating for a specified program the relative frequency with which it actually executes in specified lengths of time, or indicating for a specified program the relative frequency of a collection of specified available potential execution times (i.e., the complement of the previous measurement), or indicating for two specified programs the relative frequency of a specified collection time intervals between the end of one of the programs and the start of the other, or lastly, indicating the number of transitions between selected pairs of programs.

Abstract: A display information processing apparatus includes a central processing unit, a dual port memory including a first storage area and a second storage area, a display address generator, a timing signal generator and a control circuit and operates such that operation of the central processing unit is stopped only when data is transferred from the first storage area to the second storage area within the dual port memory. Data to be displayed is transferred only from the second storage area to a display device.

Abstract: A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent microprogam counters. The background tests are run during processor idle time and the operability tests are executed at processor turn-on. The organization of the microdiagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.

Abstract: In a computer network system having a plurality of on-line connected computer systems, each computer system has means to monitor the amount of jobs of its own computer system. Each computer system requests a job to another computer system when the amount of jobs of its own computer system is in short, and the requested computer system transfers a job to the requesting computer system if the amount of jobs of the requested computer system is enough. Each computer system also requests transfer-out of a job to another computer system when the amount of jobs of its own computer system is over, and the requested computer system accepts the request if the amount of jobs of its own computer system is not full, and the requesting computer system transfers the job to the accepting computer system. In this manner, loads to the computer systems are distributed.

Abstract: A hidden fault bit apparatus for a self-organizing digital processor system utilizing a single bit of non-volatile memory to store a hidden fault bit in each digital processor unit of the system. The hidden fault bit indicates that the digital processor which contains it, is believed to contain a hidden fault and therefore, should not participate in the self-organization process.

Abstract: An integrated circuit memory includes processing capability on the same chip, on one or both of an address path and data path between a set of access registers and a memory array so that an address can be generated, checked or manipulated and/or data can be manipulated or compared with a reference pattern of data.

Abstract: A driver module is provided which cooperates with and drives a hardware interface to a two-way communication and control system. The driver module also performs a number of error checking functions in connection with each message sent out by the master so that faulty messages are not placed on the communication and control network.

Abstract: A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code.

Abstract: A plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a hardware register to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory.

Abstract: In a process for interconnecting microprocessors, a master microprocessor (1) transmits a character. All the slave microprocessors receive it in a register (4). If processing is in progress in the slave (2) for which it is intended, the character is masked until the processing is finished. After the processing, the slave microprocessor (2) recognizes it, removes it from the register (4) and loads this latter with an echo intended for the master microprocessor (1), allowing it to transmit a new character.

Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional fields (CS, FS) carrying the encoding, in Modified Berger code, of the allocation address of the microinstruction itself and of the following one. The microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM). The two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences represent unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).

Abstract: A plesiochronous matching apparatus has a redundant system including two equipments of the same structure, that is, an on-line equipment (the reference character thereof being accompanied by "a") and a non on-line equipment (the reference character thereof being accompanied by "b"). When the on-line equipment (a) operates normally, the non on-line equipment (b) is made to synchronize with the on-line equipment (a), so that the non on-line equipment (b) is brought into a standby state. Immediately after that, the synchronization connection is dissolved and the non-on-line equipment operates independently of the on-line equipment. The above stated synchronization connection and the dissolution thereof are performed by a synchronization control circuit (57).

Abstract: A data recorder employs a disk record having a spiral track with either magnetically or optically sensible indicia. A normal mode of operation is to repeatedly scan one turn or circumvolution of the spiral track for emulating a circularly closed track. The recorder responds to received commands from a utilization device to tailor the disk access and recovery operations to the received command based upon command parameters and current status of the disk record. Electrical circuit and programming arrangements for effecting the controls are disclosed.