Abstract: A thin film transistor includes a substrate, a semiconductor layer on the substrate, a first insulating layer covering the substrate and the semiconductor layer, a first gate electrode on the first insulating layer and overlapping the semiconductor layer, a second insulating layer covering the first gate electrode and the first insulating layer, a second gate electrode on the second insulating layer and overlapping the semiconductor layer and the first gate electrode, a third insulating layer covering the second gate electrode, a first contact hole defined in the first insulating layer, the second insulating layer and the third insulating layer, and through which a portion of the semiconductor layer is exposed, and a source electrode and a drain electrode connected to the semiconductor layer through the first contact hole.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract: A package includes a die stack that includes at least two stacked dies, and a Thermal Interface Material (TIM). The TIM includes a top portion over and contacting a top surface of the die stack, and a sidewall portion extending from the top portion down to lower than at least one of the at least two stacked dies. A first metallic heat-dissipating feature is over and contacting the top portion of TIM. A second metallic heat-dissipating feature has a sidewall contacting a sidewall of the sidewall portion of the TIM.

Abstract: A TFT array substrate having compensated gate signal delays is disclosed. The TFT array substrate includes a plurality of gate lines, a plurality of data lines insulatedly intersecting with the plurality of the gate lines, and a plurality of TFT switches, each of which is connected with one of the gate lines and one of the data lines. The TFT array substrate also includes a plurality of driving units, where the driving units are located at both ends of the gate lines, and each of the driving units is connected with at least one gate line to drive the TFT switches connected to the at least one gate line.

Abstract: A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped groove, a second V-shaped groove and a third V-shaped groove formed in the substrate, a first cloak-shaped active region over the first V-shaped groove, wherein a top surface of the first cloak-shaped active region comprises a first slope, a second cloak-shaped active region over the second V-shaped groove, wherein a top surface of the second cloak-shaped active region is triangular in shape and a third cloak-shaped active region over the third V-shaped groove, wherein a top surface of the third cloak-shaped active region comprises a second slope.

Abstract: An image pickup apparatus includes: an image pickup device disposed in a first principal surface of a silicon substrate, the image pickup device sensing infrared light; an electrode pad disposed on the first principal surface; a front-face wiring connecting the image pickup device and the electrode pad; an external connection terminal disposed on a second principal surface of the silicon substrate; a back-face wiring connecting the electrode pad and the external connection terminal via a substrate through-hole extending from the second principal surface side through the silicon substrate to a back face of the electrode pad; and a light blocking layer disposed on the second principal surface, the light blocking layer covering a trench portion surrounding the image pickup device and a region surrounded by the trench portion.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

Abstract: A method for processing a silicon substrate, comprising the steps of providing a silicon substrate having a first surface and a second surface, forming a non-penetrated hole extending from the first surface toward the second surface side in the silicon substrate, sticking a sealing tape comprising a support member and an adhesive layer on the first surface and filling at least part of the non-penetrated hole with the adhesive layer, performing reactive ion etching from the second surface toward the first surface side to allow the reactive ion etching to reach the adhesive layer filled in the non-penetrated hole and to expose the adhesive layer, and peeling the sealing tape from the silicon substrate to form a through hole in the silicon substrate.

Abstract: There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion.

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: A light emitting device includes a support member, a light emitting element, and an underfill material. The support member includes an insulating member and positive and negative electrically conductive wirings arranged on the insulating member. The electrically conductive wirings are insulated and separated from each other by an insulating region arranged between the positive and negative electrically conductive wirings. The insulating separation region includes a first region disposed on an outer side with respect to the light emitting element and a second region disposed directly under the light emitting element. The first region includes an underfill arranging portion in which an interval between the electrically conductive wirings is wider than in the second region. The underfill material is arranged to extend from the underfill arranging portion to the second region in a space formed between the support member and the light emitting element.

Abstract: An anti-diffusion layer, a preparation method thereof, a thin-film transistor (TFT), an array substrate and a display device are provided, involve the display device manufacturing field and can resolve problem that a high atmosphere temperature is need in process of preparing a tantalum dioxide anti-diffusion layer by PVD or CVD, which causes the gate electrode to volatilize and affect the performance of a display device. The method for preparing the anti-diffusion layer comprises: placing a conductive base (1) and a cathode (4) in a electrolytic solution (3), taking the conductive base (1) as an anode, and forming a tantalum dioxide anti-diffusion layer on the conductive base (1) after energizing.

Abstract: An image sensing module includes an image sensing unit, a light transmitting unit, a substrate unit and lens unit. The image sensing unit includes an image sensing element having an image sensing area on the top side of the image sensing element. The light transmitting unit includes a light transmitting element supported above the image sensing element by a plurality of support members. The substrate unit includes a flexible substrate disposed on the image sensing element and electrically connected to the image sensing element through a plurality of electrical conductors, and the flexible substrate has at least one through opening for receiving the light transmitting element. The lens unit includes an opaque holder disposed on the flexible substrate to cover the light transmitting element and a lens assembly connected to the opaque holder and disposed above the light transmitting element.

Abstract: A method for depositing a film is provided. In the method, an object to be processed is accommodated in a process chamber, and an insulating film made of a polymer thin film is deposited on a surface of the object to be processed by supplying a first source gas composed of an acid anhydride and a second source gas composed of a diamine into the process chamber that is evacuated. Next, the insulating film is modified so as to have a barrier function by stopping the supply of the second source gas into the process chamber and continuously supplying the first source gas into the process chamber.

Abstract: The present invention relates to an organic light-emitting display device and a method of fabricating the same. The device may include a base substrate, a thin-film transistor disposed on the base substrate, an organic light-emitting device including a first electrode connected to the thin-film transistor, an organic pattern disposed on the first electrode, and a second electrode disposed on the organic pattern. The device further includes an auxiliary electrode including a connection part and a non-connection part, the connection part being connected to the second electrode. The width of the connection part may be less than that of the non-connection part, when measured in the direction perpendicular to a current flow.

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract: The integration of bilayer graphene with an absorption enhancing sub-wavelength antenna provides an infrared photodetector capable of real-time spectral tuning without filters at nanosecond timescales.

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.