Abstract: An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.

Abstract: A TFT array substrate, a fabrication method thereof and a display device. The TFT array substrate, comprising: gate lines (19), data lines (20) and a plurality of pixel units, each pixel unit comprises: a common electrode line (11), a gate insulating layer (16), a passivation layer (17) and a pixel electrode (12) in this order, wherein a backup common electrode line (41) is disposed at a position between the gate insulating layer (16) and the passivation layer (17) and opposite to the common electrode line (11), the backup common electrode line (41) is electrically insulated from the data line (20). The TFT array substrate with this structure can avoid the short circuit between the pixel electrode (12) and the common electrode line (11).

Abstract: Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

Abstract: An organic light emitting display panel including a partition wall to prevent different organic light emitting materials from being mixed with each other between adjacent light emitting areas. The partition wall may protrude from a surface of a pixel definition layer or a first common layer. Accordingly, desired light colors are generated by organic light emitting patterns respectively disposed in the light emitting areas.

Abstract: The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.