Patents Examined by Christine T. Tu
  • Distributed CRC polar codes
    Patent number: 11196445
    Abstract: A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: December 7, 2021
    Assignees: Nokia Technologies Oy, Alcatel Lucent
    Inventors: Keeth Saliya Jayasinghe, Yu Chen, Dongyang Du, Jie Chen
  • Computer-implemented method for error-correction-encoding and encrypting of a file
    Patent number: 11196447
    Abstract: A computer-implemented method for error-correction-encoding and encrypting of a file is provided. The file is split into at least two blocks. The first block is encrypted using a given encryption key. The encrypted first block is encoded twice using a first and second forward error correction code of the first block. Each subsequent block is encrypted by performing an algebraic operation. The encrypted block is encoded twice using a first and second forward error correction code for this block, wherein a cryptographic indexing function provides a set of indices used by the second forward error correction code to produce the second encoded chunk. The first encoded chunks of each encrypted block are outputted. The computer-implemented method enables secure transmission of a file content between low power devices.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 7, 2021
    Inventors: Jorge Cuellar, Tiago Gasiba, Martin Wimmer
  • Polar decoder with LLR-domain computation of f-function and g-function
    Patent number: 11190221
    Abstract: A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 30, 2021
    Assignee: Accelercomm Limited
    Inventors: Robert Maunder, Matthew Brejza, Shida Zhong, Isaac Perez-Andrade, Taihai Chen
  • Memory system, memory module, and operation method of memory system
    Patent number: 11188417
    Abstract: An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Hoiju Chung
  • Storage controller for correcting error, storage device including the same, and operating method thereof
    Patent number: 11184030
    Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heeyoul Kwak, Jae Hun Jang, Hong Rak Son, Dong-Min Shin, Geunyeong Yu, Kangseok Lee, Hyunseung Han
  • Parallel turbo decoding with non-uniform window sizes
    Patent number: 11184109
    Abstract: A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 23, 2021
    Assignee: Accelercomm Limited
    Inventors: Robert Maunder, Matthew Brejza, Luping Xiang
  • Communication method and apparatus using polar codes
    Patent number: 11177834
    Abstract: A communication device includes: an encoder that encodes an input vector to output a codeword using a generator matrix of polar code; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices; and a controller that is configured to: a) select at least one check bit index from the frozen set in descending order of row weights of the generator matrix and in descending order of index reliabilities of the input vector; b) select at least one non-frozen bit index from the non-frozen set to compute at least one check bit from at least one bit of information bits at the at least one non-frozen bit index; and c) put the at least one check bit at the at least one check bit index.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 16, 2021
    Assignee: NEC CORPORATION
    Inventors: Prakash Chaki, Norifumi Kamiya
  • Recast repetitive messages
    Patent number: 11177907
    Abstract: A method, computer system, and a computer program product for recasting repetitive messages is provided. Embodiments may include receiving, by a processor, a message. Embodiments may include determining, by the processor, whether the received message is repetitive. Embodiments may include rating, by the processor, an importance level of the received message. Embodiments may include determining a preference for recasting the received message.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul R. Bastide, Matthew E. Broomhall, Robert E. Loredo
  • Inspection device
    Patent number: 11169208
    Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 9, 2021
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Matthias Klemm
  • Method, device, data storage system, and computer product for error injection
    Patent number: 11157378
    Abstract: Error injection techniques involve, while a data storage system is in an error injection mode, injecting information representing an error of a storage device array into a first switch, such that the information representing the error is passed from a first downstream port of the first switch to a computing device through a second switch, the first and second switches being connected to the storage device array via downstream ports, and the first downstream port being connected to a second downstream port of the second switch; and determining error handling capability of the data storage system by obtaining a handling result of the information representing the error from the computing device. Accordingly, errors from storage devices can be simulated to facilitate detecting error handling in the entire I/O path comprehensively.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Min Zhang
  • Transmission method, reception method, transmitter, and receiver
    Patent number: 11153036
    Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: October 19, 2021
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Chip testing method, device, electronic apparatus and computer readable medium
    Patent number: 11145386
    Abstract: A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timing specifications of the chip to be tested; selecting a test pattern from a test pattern library according to the language rule and the product and timing specifications; generating a test code according to the product and timing specifications and the test pattern; and automatically testing the chip to be tested by using the test code. The chip testing method, device, electronic apparatus and computer readable medium can automatically generate a big-data test code for complex memories, and rapidly generate, in a standardized way, test codes for DDR4 memories of different specifications, thereby improving the efficiency of chip product verification analysis.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: October 12, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Ruei-Yuan Guo
  • Test apparatus and test method
    Patent number: 11137446
    Abstract: A test apparatus is configured to test a DUT that does not support synchronous control from an external circuit. A main controller is configured based on an architecture that tests a device by synchronous control with the main controller itself as the master. A MIU is configured as an interface between the main controller and the DUT. The MIU establishes asynchronous control between it and the DUT with the DUT as the master, and establishes control between it and the main controller with the main controller as the master.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANTEST CORPORATION
    Inventors: Shuichi Inage, Kazuhiro Iezumi, Tomoyuki Itakura, Keisuke Kusunoki, Yoshihiro Kato, Kazuhiro Tsujikawa, Naoya Kimura, Yuki Watanabe, Yuichiro Harada, Koji Miyauchi
  • Method of testing memory device employing limited number of test pins and memory device utilizing same
    Patent number: 11125816
    Abstract: A method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pin.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 21, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaodong Xu, Xiangming Zhao, Shunlin Liu, Yi Chen
  • Memory device, semiconductor device, and semiconductor system
    Patent number: 11113145
    Abstract: A memory device includes a plurality of pages. Each page includes a data region configured to store data, an error correction code (ECC) region configured to store ECC data that is used to detect and correct one or more errors occurring in the data stored in the data region, and a metadata region configured to store a write count of a corresponding page.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Park
  • Selective sampling of a data unit during a program erase cycle based on error rate change patterns
    Patent number: 11106532
    Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Harish R Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Imprint management for memory
    Patent number: 11094394
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Iterative decoder performance prediction using machine learning
    Patent number: 11088712
    Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, David Avraham, Eran Sharon
  • Memory apparatus and data accessing method thereof
    Patent number: 11088711
    Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 10, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
  • Semiconductor memory devices and memory systems
    Patent number: 11068340
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanguhn Cha, Hoyoung Song, Myungkyu Lee, Sunghye Cho