Abstract: A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

Abstract: Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

Abstract: Disclosed is a system comprising a memory component having a plurality of memory cells capable of being in a plurality of states, each state of the plurality of states corresponding to a value stored by the memory cell, and a processing device, operatively coupled with the memory component, to perform operations comprising: obtaining, for the plurality of memory cells, a plurality of distributions of threshold voltages, wherein each of the plurality of distributions corresponds to one of the plurality of states, classifying each of the plurality of distributions among one of a plurality of classes, generating a vector comprising a plurality of components, wherein each of the plurality of components represents the class of a respective one of the plurality of distributions, and processing, using a classifier, the generated vector to determine a likelihood that the memory component will fail within a target period of time.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

Abstract: Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.

Abstract: In a method for soft buffer handling in a user equipment in a wireless communication system, performing the steps of receiving (S100) a transmission, identifying (S101) overlapping positions for non-zero soft values in a soft buffer and received transmission soft values, copying and storing (S102) identified overlapping non-zero soft values or received transmission soft values, and combining (S103) soft buffer with received transmission.

Abstract: A method by a network device for detecting data in a data stream. The method includes receiving the data stream, where the data stream includes a sequence of original characters, generating a sequence of type-mapped characters corresponding to the sequence of original characters, converging each of two or more consecutive occurrences of a first character in the sequence of type-mapped characters into a single occurrence of the first character, inserting beginning/ending of segment indicators in the sequence of type-mapped characters, searching for occurrences of one or more predefined sequences of characters in the sequence of type-mapped characters, and responsive to finding an occurrence of any of the one or more predefined sequences of characters, extracting a sequence of characters in the sequence of original characters corresponding to the predefined sequence of characters found in the sequence of type-mapped characters.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.

Abstract: A memory system having a mode indicator, a set of hardware resources, a set of media, and a controller. When the mode indicator identifies a factory mode, a first portion of the hardware resources is reserved for performance of factory functions by the controller and a second portion of the hardware resources is allocated for performance of normal functions. When the mode indicator identifies a user mode, both the first portion and the second portion are allocated for the performance of the normal function. The normal functions are performed by the controller to at least store data in and retrieve data from the set of media in response to requests from a host system.

Abstract: A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). The memory supports error-detection and correction (EDC) techniques by allocating a fraction of DRAM storage to information calculated for each unit of stored data that can be used to detect and correct errors. An interface between the DRAM cache and NVM executes a wear-leveling scheme that aggregates and distributes NVM data and EDC write operations in a manner that prolongs service life.

Abstract: A data processing system may include: a host; and a memory system including a plurality of memory units and a controller coupled to the plurality of memory units. The controller may include a memory manager suitable for acquiring characteristic data from serial presence detect (SPD) components in the plurality of memory units when power is supplied, providing the characteristic data to the host, setting an operation mode of each of the plurality of memory units based on the characteristic data, and performing memory training, and the host may perform interface training with the controller.

Abstract: A processing device reads data from a memory device in response to a received request and performs a first error control operation on the data based on an initial operating characteristic to correct one or more errors in the data. The processing device determines that the first error control operation based on the initial operating characteristic failed to correct the one or more errors in the data, modifies the initial operating characteristic to generate a modified operating characteristic and performs a second error control operation on the data based on the modified operating characteristic to correct the one or more errors in the data.

Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

Abstract: An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.