Abstract: A direct memory access (DMA) engine may receive a first indication that memory descriptors for a DMA operation are ready to be fetched from a memory. The DMA engine may prefetch the memory descriptors from the memory without waiting for memory locations specified in the memory descriptors to be ready for access. The DMA engine may receive a second indication that the memory locations specified in the memory descriptors are ready to be accessed. The DMA engine may execute the DMA operation based on the memory descriptors upon receiving the second indication.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.

Abstract: A control apparatus that bidirectionally communicates with a control unit based on a preset time-sharing method includes: a plurality of devices each installed on a different substrate; a communication controller daisy-chained to the control unit via a bus line through which bidirectional communication of communication data is performed, the communication data having a data structure having a band in which data to be communicated between the plurality of devices is superimposable; and a cable configured to connect at least one device of the plurality of devices to the communication controller.

Abstract: An information handling resource assembly may include an information handling resource implemented with a circuit board having a plurality of locating features formed therein, a receptacle connector having a plurality of mounting features, each of the mounting features formed at respective ends of the receptacle connector, and a housing for housing the information handling resource and the receptacle connector and comprising a plurality of standoffs extending from a surface of the housing, each particular standoff comprising a receiving feature for receiving a respective fastener, such that mechanical engagement of a plurality of fasteners wherein each respective fastener is passed through a respective locating feature of the plurality of locating features, passed through a respective mounting feature of the plurality of mounting features, and received by the receiving feature of the particular standoff mechanically loads the information handling resource and the receptacle connector in a fixed position relat

Abstract: Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities.

Abstract: A method for integrating into a data transmission a number of I/O modules connected to an I/O station in accordance with a configuration for processing data assignable in accordance with this configuration, includes activating an integration mode, checking whether a target configuration for connecting a number of I/O modules to the I/O station for processing primary data is stored in a memory, checking whether the target configuration can be found on the basis of analyzed connected I/O modules, assigning each I/O module required for finding the target configuration to the target configuration, assigning each I/O module not required for finding the target configuration, to a new configuration for processing data, operating the I/O station with each I/O module assigned to the target configuration in accordance with the target configuration, and operating the I/O station with each I/O module assigned to the new configuration independently of and/or in addition to the target configuration in accordance with the n

Abstract: A data processing method using a DMA, the method comprising: deriving a waiting time of a waiting time of a first DMA operation for a first computation task and a waiting time of a second DMA operation for a second computation task, deriving a MO value of the first DMA operation and a MO value of the second DMA operation based on the waiting time of the first DMA operation and the waiting time of the second DMA operation, and performing the first DMA operation based on the MO value of the first DMA operation, and performing the second DMA operation based on the MO value of the second DMA operation.

Abstract: Provided is a method for shifting data within a memory, which is performed by a direct memory access (DMA) controller, and which includes receiving a task associated with an operation of shifting target data stored in a first area of a memory connected to the DMA controller to a second area of the memory, based on the task, generating sub-tasks associated with operations of shifting data chunks divided from the target data to the second area, determining data chunk groups each including at least one data chunk by grouping the data chunks, determining a priority of each of the data chunk groups based on an address of the first area and an address of the second area, and shifting the data chunk groups to the second area in sequence according to the determined priority.

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, including a stored-program processing circuit, a first network interface circuit, and a first memory module. The first memory module may include a first memory die, and a controller. The controller may be connected to the first memory die through a memory interface, to the stored-program processing circuit through a cache-coherent interface, and to the first network interface circuit.

Abstract: Provided are a distributed parallel computing based graph computing method, a distributed parallel computing system and a computer readable medium. A graph computing method comprises: obtaining data of a graph to be computed, the graph comprising a plurality of vertices and edges; storing the graph according to a compressed sparse row format, and storing the graph in a sparse matrix form, wherein all adjacent edges having a same vertex are continuously stored, and an offset array is used to support an index function thereof; and for subgraphs in which the degrees of both source vertices and target vertices are greater than a predetermined threshold, in forward graphs, performing segmentation according to target vertices, i.e., the column of a matrix, and in reverse graphs, performing segmentation according to source vertices, i.e.

Abstract: A device (125) that may configure itself is disclosed. The device (125) may include an interface (305) that may be used for communications with a chassis (105). The interface (305) may support a plurality of transport protocols (330, 355, 345, 350). The device (125) may include a Vital Product Data (VPD) reading logic (310) to read a VPD (130) from the chassis (105) and a built-in self-configuration logic (315) to configure the interface (305) to use one of the transport protocols (330, 355, 345, 350) and to disable alternative transport protocols (330, 355, 345, 350), responsive to the VPD (130).

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.

Abstract: A test and measurement instrument includes a processor configured to execute instructions that cause the processor to: receive a bus auto-detect signal; receive signals from a bus connected to the test and measurement instrument; and apply machine learning to the signals from the bus to output a predicted a bus type; at least one memory to store the instructions and data used in the machine learning, and a display to display information for a user including the predicted bus type. A method of automatically detecting a bus type includes receiving a bus auto-detect signal when a bus is connected to a test and measurement instrument, receiving signals from the bus at a processor, and using the processor to apply machine learning to the signals from the bus to predict a bus identity.

Abstract: A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.

Abstract: Chunked data transfers may include: receiving, from an initiator, a read command for first data stored in a storage system; allocating a first buffer of a predefined size; until all of the first data has been sent to the initiator: loading a portion of the first data from the storage system into the first buffer; and sending, to the initiator, the portion of the first data in the first buffer.

Abstract: An example network device includes one or more hardware resources; a physical interface for receiving a hardware component; a memory; and one or more processors implemented in circuitry and configured to: receive the hardware component that has been coupled to the physical interface of the network device; receive data for an application programming interface (API) for the hardware component; store the data for the API to the memory; and execute the data for the API to grant the hardware component secure access to the hardware resources of the network device via the API. The hardware component may be an optical network interface. The resources may be raw registers of the network device. The processors may further tune the hardware component according to configuration for the network device, such as power management configuration for the network device, or the network device itself.

Abstract: A computing system comprises an abstracted interface comprising a plurality of sub-interfaces differently configured from one another in terms of underlying communication hardware and software supported by the sub-interface. The abstracted interface further comprises a unified interface communicatively coupled with each of the sub-interfaces. Each sub-interface is configured to abstract away its respective underlying communication hardware and software from the unified interface. The unified interface is further configured to provide communication between the communication service and the control center. A monitoring service is configured to observe communication activity and output one or more communication parameters. A data prioritization policy is chosen based upon the one or more communication parameters. Data is selected for transmission based upon the data prioritization policy.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface coupled to the first transmission interface. The first transmission interface and the second transmission interface are both flash memory interface.

Abstract: In accordance with an embodiment, a direct memory access (DMA) system includes input interface circuitry configured to receive a data packet of a sensor from a source memory. The DMA system comprises processing circuitry configured to determine whether the data packet comprises a synchronized data frame and, when it is determined that the data packet comprises a synchronized data frame, extract a payload of the synchronized data frame. The DMA system comprises output interface circuitry configured to send the payload or data derived from the payload to a destination memory.