Abstract: Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and a save and forward module connected to the interconnect module and the bus interface, in which the save and forward module includes a slave port that receives a transaction from one of the interconnect module or the bus interface, a data buffer that temporarily stores at least a portion of the transaction, and a master port that transmits the transaction stored in the data buffer to the other one of the interconnect module or the bus interface, and the transaction is divided into predetermined units and transmitted.

Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.

Abstract: A Computing based control system for managing signals from a variety of input devices equipped with sensors, such as resistive potentiometers pedals, load cell buttons, pressure sensitive, optical, capacitive, magnetic, voice activated, proximity, sonar and other types of sensors or I/O devices. The system comprises of at least one Hub or electronic control system including one or more processing units, memory units for storing instructions and saving data, and other components such as long-term storage devices, display units, networking, interfaces and more, with the system receiving information from the sensors, processing inputs and dynamically adjusting a range of control parameters, including but not limited to cursor speed and DPI settings. The system can communicate multi-directionally with multiple peripherals, allowing real-time customization and refinement of settings and output characteristics for sensor devices.

Abstract: Probation of direct memory access (DMA) device used for direct device assignment. A virtualization computer system identifies a peripheral device as being removed from a direct assignment to a first operating context of a virtualization environment. The peripheral device is DMA capable. The virtualization computer system assigns the peripheral device to a second operating context of the virtualization environment and initiates a device validation against the peripheral device. Based on the device validation indicating that the peripheral device is normal, the virtualization computer system reassigns the peripheral device to a third operating context of the virtualization environment. Based on the device validation indicating that the peripheral device is abnormal, the virtualization computer system excludes the peripheral device from assignment to a third operating context of the virtualization environment.

Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.

Abstract: In a method for transfer of USB data in a data stream, which includes streaming data, the streaming data and the USB data, which includes a number of USB packets with a first number of bits, is received. The USB data is divided to create a number of transfer packets with a second number of bits of USB data. A transfer packet is inserted into the data stream, and the assembled data stream is transferred. An interruption pattern is added to at least an initial transfer packet to signal that USB data is present in the data stream.

Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.

Abstract: Embodiments described herein provide SPI systems that can accommodate more peripheral devices on a serial data signal line. The present disclosure relates to various configurations of SPI communication interfaces that operably connect one or more peripheral devices serially to a controller device. The configurations of serially-connected peripheral devices can enable more peripheral devices to be supported on a serial data signal line in each SPI system. The present disclosure reduces or eliminates the limitation regarding the driving capability of the controller device or the peripheral devices. The present disclosure further reduces the restriction regarding the pin count requirement for the select signals.

Abstract: A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit implementing a plurality of data paths coupled to respective ones of the plurality of client circuits for conveying the read completion data as scheduled by the read scheduler circuit.

Abstract: A memory system includes a nonvolatile memory and a memory controller including a bus, a cache memory, a direct memory access controller, a first search circuit, a second search circuit, and a transfer control circuit. The direct memory access controller transfers cache target data stored in the nonvolatile memory to the cache memory. The second search circuit searches the cache target data that is being transferred. The transfer control circuit assigns, in response to the second search circuit detecting a search hit, to the transfer control circuit and the second search circuit, a bus right which has been assigned at least to the cache memory for the transfer of the cache target data to the cache memory, and obtains, by using the assigned bus right, a search result from the second search circuit via the bus.

Abstract: A method and apparatus for transmitting data based on peripheral component interconnect express (PCIe) are disclosed. The method includes receiving, at an endpoint (EP), a doorbell (DB) message transmitted from a root complex (RC) via a PCIe connection between the endpoint (EP) and the RC; based on the DB message, transmitting, by polling of a processor of the EP, a read request message to a direct memory access (DMA) controller of the EP; and in response to reception of the read request message by the DMA controller, reading, by the DMA controller, data to be transmitted from a memory of the RC and recording read data into a memory of the EP.

Abstract: An electronic device comprising a plurality of chiplets is disclosed. The electronic device comprises a first chiplet that generates a transaction, a second chiplet that receives the transaction, and at least one third chiplet that relays the transaction, wherein the first chiplet determines a route path for the transaction that passes through the at least one third chiplet, and transmits the transaction through the determined route path for the transaction.

Abstract: An image processing system, includes an image sensor, a bus structure coupled to the image sensor, and a system memory coupled to the image sensor via the bus structure. A direct memory access (DMA) controller is coupled to the bus structure. The DMA controller includes in-line logic hardware configured to retrieve raw pixel data from the image sensor, and internally process the retrieved raw pixel data thereby providing processed pixel data.

Abstract: An infrastructure management (IM) system including first and second communication modules. A user device is communicatively coupled to the first communication module and a target server is communicatively coupled to the second communication module via a USB port. One or more first messages may be communicated over the USB port to the target server using a first communication protocol. One or more second messages may be communicated over the USB port to the target server using a second communication protocol.

Abstract: A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.

Abstract: An A/D conversion control circuit includes a scan group control unit and a FIFO unit. The scan group control unit includes an input reception unit and an arbitration unit. The FIFO unit includes a plurality of pointer control units provided correspondingly to the plurality of FIFO memories, respectively. Each of the pointer control units clears or changes a position of a write pointer/read pointer of the corresponding FIFO memory at the timing of at least any of the start, interruption, and/or restart of the corresponding scan group according to the priority of the scan group.

Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

Abstract: A data processing method using a scatter gather direct memory access (SG DMA), the method comprising: obtaining information for a rule table for specific subtasks of a SG DMA from a host, deriving the rule table for the specific subtasks based on the information, deriving source addresses, destination addresses and data sizes for the specific subtasks based on the rule table, and performing a SG DMA operation to transfer data of the data sizes located at the source addresses of a first memory to data spaces of the data sizes located at the destination addresses of a second memory.

Abstract: A method for use in a storage processor, comprising: receiving an I/O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I/O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.