Abstract: A system comprising a traffic handler comprising circuitry to determine that data of a memory request is stored remotely in a memory pool; generate a packet based on the memory request; and direct the packet to a path providing a guaranteed latency for completion of the memory request.

Abstract: There is provided a detection system including a detection device and a post processor. The detection device and the post processor exchange data therebetween using a predetermined communication protocol. The detection device outputs at least one of calculated data and raw data to the post processor in response to each polling according to a request from the post processor. The raw data is provided to the post processor for the machine learning.

Abstract: An apparatus is provided that includes a network interface to transmit and receive data packets over a network; a memory including one or more buffers; an arithmetic logic unit to perform arithmetic operations for organizing and combining the data packets; and a circuitry to receive, via the network interface, data packets from the network; aggregate, via the arithmetic logic unit, the received data packets in the one or more buffers at a network rate; and transmit, via the network interface, the aggregated data packets to one or more compute nodes in the network, thereby optimizing latency incurred in combining the received data packets and transmitting the aggregated data packets, and hence accelerating a bulk data allreduce operation. One embodiment provides a system and method for performing the allreduce operation. During operation, the system performs the allreduce operation by pacing network operations for enhancing performance of the allreduce operation.

Abstract: This disclosure describes processes for performing direct memory access (“DMA”) between memory of a host and memory of a smart network interface controller (“SNIC”) connected to a bus of the host. The host runs a host thread in a processor of the host and the SNIC runs a SNIC thread in a processor of the SNIC. The host thread and the SNIC thread facilitate direct access of the SNIC thread to memory locations in the memory of the host. The SNIC thread can fetch data directly from and/or write data directly to the memory locations of the memory of the host over the bus.

Abstract: Generally disclosed herein is an approach for enabling the connection of non-PCIe accelerators as PCIe devices using a Peripheral Component Interconnect Express (PCIe) abstraction layer (“PAL”). Once the operating system accesses and configures any on-SoC devices and accelerators using standard PCIe APIs, all PCIe configuration transactions may be routed to the PAL. The PAL's firmware may present the operating system with a virtual PCIe space that contains all available SoC PCIe and non-PCIe devices. The firmware of the PAL may translate PCIe configuration transactions into device-specific configuration transactions.

Abstract: A system that includes dynamic DMA buffer management.

Abstract: Techniques are disclosed for systems and methods associated with a modular electrical power distribution system with module detection. A modular electrical power distribution system may include a plurality of controllers, a shared serial communication bus between the plurality of controllers, and a module detection signal line coupled through the plurality of controllers. The plurality of controllers may include a master controller, a power input controller, and one or more load controllers disposed between the master controller and the power input controller.

Abstract: A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.

Abstract: Multicast reading of compute module registers is disclosed. A cryptocurrency miner comprises a serial bus, compute modules, and a miner controller coupled to the compute modules via the serial bus. The miner controller issues a multicast read command via the serial bus and receives values from respective registers of a first plurality of compute modules. The miner controller may initialize the compute modules with register set configurations that identify respective registers and latencies for returning values from such registers.

Abstract: An information transmission method is provided, including: A control device obtains a second universal serial bus video class UVC port and a second virtual network port based on configuration of a universal serial bus USB port of the control device. The control device determines address information of a camera device, where a first UVC port and a first virtual network port are configured on the camera device, and the first UVC port and the first virtual network port are obtained based on configuration of a USB port of the camera device. The control device sends the address information to the camera device through a UVC channel, where the UVC channel is established based on the first UVC port and the second UVC port.

Abstract: A data storage device is disclosed. The data storage device comprises a data storage unit, a data transmission interface, and a microprocessor. The data transmission interface is connected to the data storage unit via a switch. The microprocessor is connected to an input and output device, and connected to the data storage unit via the switch. The microprocessor is configured with an embedded system. When a connection between the data transmission interface and the data storage unit is conducted via the switch, a host is able to read data from or write to the data storage unit via the data transmission interface. Otherwise, when a connection between the microprocessor and the data storage unit is conducted via the switch, the embedded system of the microprocessor can execute an input and output process between the input and output device and the data storage unit.

Abstract: A device includes a direct memory access (DMA) controller comprising DMA channels, a bridge circuit configured to couple the DMA channels to memory channels coupled to respective memory modules, and a local memory unit. The DMA controller is configured to transfer tensor data between the local memory unit and the memory modules via the DMA channels and the memory channels using concurrent data transactions, the tensor data is stored and addressed as parts of a single tensor in the local memory unit, and the tensor data is interleaved onto the memory modules and is stored and addressed as sub-tensors in respective memory modules.

Abstract: Methods, systems, and devices for memory systems having a selectively interfaceable memory subsystem are described. A memory system may include the memory subsystem that may be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem may include a plurality of ports each capable of communicating with the host system using different interfaces. The memory subsystem may be dynamically configurable to perform different functions based on the demands of the host system. In some examples, memory systems described herein may include a first memory subsystem to provide nonvolatile storage to the host system, a second memory subsystem to provide volatile storage to the host system, and a third memory subsystem configurable to provide volatile storage or nonvolatile storage or both to the host system.

Abstract: A data moving method, a direct memory access apparatus, and a computer system are disclosed. The data moving method is used for a neural-network processor, the neural-network processor includes at least one processing unit array, and the method includes: receiving a first instruction, wherein the first instruction indicates address information of target data to be moved, and the address information of the target data is obtained based on a mapping relationship between the target data and at least one processing unit in the processing unit array; generating a data moving request according to the address information of the target data; and moving the target data for the neural-network processor, according to the data moving request.

Abstract: A method of training a physical interface between a first device and a second device includes performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes; performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group; determining a lane group based on a result of the first training and a result of the second training; and setting the second device so that the determined lane group is used for the physical interface.

Abstract: A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.

Abstract: In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Abstract: One example discloses a communications device, including: an interface port, configured to couple the communications device to another device; a transmitter configured to transmit signals on the interface port; a receiver configured to receive signals on the interface port; and a switch configured to short the interface port to a reference potential after the transmitter transmits signals on the interface port.

Abstract: An electronic system includes an auxiliary processor. The auxiliary processor includes a remapping device which receives data through a direct memory access (DMA, a register unit which stores the data, and processing logic which transmits operating status information to the remapping device. The remapping device remaps position information in which the data is stored in the register unit on the basis of the operating status information.

Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.