Abstract: An image processing system, includes an image sensor, a bus structure coupled to the image sensor, and a system memory coupled to the image sensor via the bus structure. A direct memory access (DMA) controller is coupled to the bus structure. The DMA controller includes in-line logic hardware configured to retrieve raw pixel data from the image sensor, and internally process the retrieved raw pixel data thereby providing processed pixel data.

Abstract: An infrastructure management (IM) system including first and second communication modules. A user device is communicatively coupled to the first communication module and a target server is communicatively coupled to the second communication module via a USB port. One or more first messages may be communicated over the USB port to the target server using a first communication protocol. One or more second messages may be communicated over the USB port to the target server using a second communication protocol.

Abstract: A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.

Abstract: An A/D conversion control circuit includes a scan group control unit and a FIFO unit. The scan group control unit includes an input reception unit and an arbitration unit. The FIFO unit includes a plurality of pointer control units provided correspondingly to the plurality of FIFO memories, respectively. Each of the pointer control units clears or changes a position of a write pointer/read pointer of the corresponding FIFO memory at the timing of at least any of the start, interruption, and/or restart of the corresponding scan group according to the priority of the scan group.

Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

Abstract: A data processing method using a scatter gather direct memory access (SG DMA), the method comprising: obtaining information for a rule table for specific subtasks of a SG DMA from a host, deriving the rule table for the specific subtasks based on the information, deriving source addresses, destination addresses and data sizes for the specific subtasks based on the rule table, and performing a SG DMA operation to transfer data of the data sizes located at the source addresses of a first memory to data spaces of the data sizes located at the destination addresses of a second memory.

Abstract: A method for use in a storage processor, comprising: receiving an I/O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I/O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

Abstract: An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer/deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and/or memory interface; and a data interconnect communicatively coupling each respective memory element and/or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and/or datagram communication over a cell-based switch fabric to and from the respective memory elements and/or memory interfaces of the plurality of inference engine clusters via the data interconnect.

Abstract: A multi-core system includes a first processor core, a first memory coupled to the first processor core, a first communication IF including a first DMA unit coupled to the first memory, a second processor core, a second memory coupled to the second processor core, a second communication IF including a second DMA unit coupled to the second memory, and an MMU. In a case where page data of a page designated as a read destination by the first processor core is stored in the second memory, the MMU causes the first DMA unit to set a first transmission descriptor based on a page number of the page. The first communication IF transmits a data request including the page number and destination data to the second communication IF according to the first transmission descriptor.

Abstract: A computer device is disclosed. In a virtualization I/O procedure, a redirection apparatus in a processor is used to implement privilege level switching in a synchronization processing procedure, to directly switch from a virtualization privilege level of a VM to a user mode of a host, and perform corresponding exception processing. In an asynchronous processing procedure, an interrupt request may be asynchronously transferred by using a virtual event notification apparatus and an interrupt controller in the processor without passing through a kernel mode of the host. In both of a synchronous processing procedure and the asynchronous processing procedure of the device, overheads generated during switching are reduced, and performance of the computer device is improved.

Abstract: A direct memory access (DMA) engine may receive a first indication that memory descriptors for a DMA operation are ready to be fetched from a memory. The DMA engine may prefetch the memory descriptors from the memory without waiting for memory locations specified in the memory descriptors to be ready for access. The DMA engine may receive a second indication that the memory locations specified in the memory descriptors are ready to be accessed. The DMA engine may execute the DMA operation based on the memory descriptors upon receiving the second indication.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.

Abstract: A control apparatus that bidirectionally communicates with a control unit based on a preset time-sharing method includes: a plurality of devices each installed on a different substrate; a communication controller daisy-chained to the control unit via a bus line through which bidirectional communication of communication data is performed, the communication data having a data structure having a band in which data to be communicated between the plurality of devices is superimposable; and a cable configured to connect at least one device of the plurality of devices to the communication controller.

Abstract: An information handling resource assembly may include an information handling resource implemented with a circuit board having a plurality of locating features formed therein, a receptacle connector having a plurality of mounting features, each of the mounting features formed at respective ends of the receptacle connector, and a housing for housing the information handling resource and the receptacle connector and comprising a plurality of standoffs extending from a surface of the housing, each particular standoff comprising a receiving feature for receiving a respective fastener, such that mechanical engagement of a plurality of fasteners wherein each respective fastener is passed through a respective locating feature of the plurality of locating features, passed through a respective mounting feature of the plurality of mounting features, and received by the receiving feature of the particular standoff mechanically loads the information handling resource and the receptacle connector in a fixed position relat

Abstract: Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities.

Abstract: A method for integrating into a data transmission a number of I/O modules connected to an I/O station in accordance with a configuration for processing data assignable in accordance with this configuration, includes activating an integration mode, checking whether a target configuration for connecting a number of I/O modules to the I/O station for processing primary data is stored in a memory, checking whether the target configuration can be found on the basis of analyzed connected I/O modules, assigning each I/O module required for finding the target configuration to the target configuration, assigning each I/O module not required for finding the target configuration, to a new configuration for processing data, operating the I/O station with each I/O module assigned to the target configuration in accordance with the target configuration, and operating the I/O station with each I/O module assigned to the new configuration independently of and/or in addition to the target configuration in accordance with the n

Abstract: A data processing method using a DMA, the method comprising: deriving a waiting time of a waiting time of a first DMA operation for a first computation task and a waiting time of a second DMA operation for a second computation task, deriving a MO value of the first DMA operation and a MO value of the second DMA operation based on the waiting time of the first DMA operation and the waiting time of the second DMA operation, and performing the first DMA operation based on the MO value of the first DMA operation, and performing the second DMA operation based on the MO value of the second DMA operation.

Abstract: Provided is a method for shifting data within a memory, which is performed by a direct memory access (DMA) controller, and which includes receiving a task associated with an operation of shifting target data stored in a first area of a memory connected to the DMA controller to a second area of the memory, based on the task, generating sub-tasks associated with operations of shifting data chunks divided from the target data to the second area, determining data chunk groups each including at least one data chunk by grouping the data chunks, determining a priority of each of the data chunk groups based on an address of the first area and an address of the second area, and shifting the data chunk groups to the second area in sequence according to the determined priority.

Abstract: A system and method for managing memory resources. In some embodiments the system includes a first server, including a stored-program processing circuit, a first network interface circuit, and a first memory module. The first memory module may include a first memory die, and a controller. The controller may be connected to the first memory die through a memory interface, to the stored-program processing circuit through a cache-coherent interface, and to the first network interface circuit.