Abstract: A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.

Abstract: An apparatus comprises a host device configured to communicate over a network with a storage system. The host device comprises a multi-path input-output (MPIO) driver configured to control delivery of input-output (TO) operations to the storage system over selected ones of a plurality of paths through the network. The MPIO driver is further configured to determine mappings between ranges of logical block addresses (LBAs) of logical storage volumes and respective ones of a plurality of cache entities of the storage system, to select, for a first IO operation comprising a first set of LBAs of a first logical storage volume, a first one of the paths associated with a first one of the cache entities, and to select, for a second IO operation comprising the first set of LBAs of a second logical storage volume, a second one of the paths associated with a second one of the cache entities.

Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.

Abstract: A method is provided for remote control. Peripheral component interconnect express (PCI-E) is used for controlling with universal serial bus (USB) type-C (USB-C). A controlling terminal inputs a control signal of switching through a user interface. The controlling terminal transfers the control signal to a PCI-E connector of an image capture unit through a first port. After being handled and transformed by a processing device, the control signal is transferred with a USB-C connector of the image capture unit to at least one controlled terminal through a second port. Thus, the image capture unit is expanded in function to obtain keyboard-video-mouse switch (KVM Switch) among the category of image capturing cards. In summary, with a remote connection, a controlling terminal remotely controls a controlled terminal while simple flow, enhanced speed, and effective cost-down are achieved.

Abstract: Programmable ultrasound probes and methods of operation are described. The ultrasound probe may include memory storing parameter data and may also include a parameter loader which loads the parameter data into programmable circuitry of the ultrasound probe. In some instances, the ultrasound probe may include circuitry grouped into modules which may be repeatable and which may be coupled together to allow data to be exchanged between the modules.

Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a non-volatile memory; a device interface circuit which receives an input/output (I/O) request from a host; and a device controller which executes a data access according to the I/O request on the non-volatile memory, and transmits an interrupt to the host a predetermined time before completion of the data access.

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

Abstract: An interrupt recovery manager detects that a compute instance has exited a state in which interrupts from one or more interrupt sources were not processed at the compute instance. The recovery manager identifies a source from which interrupts may have been missed by the compute instance, and causes an indication of a potential missed interrupt from that source to be delivered to the compute instance.

Abstract: The present technology relates to a communication device and a control method, in which the variety of connection modes between electronic apparatuses can be increased. Provided are: a detection target mechanism detected when the first electronic apparatus is connected to a second electronic apparatus that receives a baseband signal output from the first electronic apparatus; a connection detecting unit adapted to detect a baseband signal output from the second electronic apparatus and to detect a connection between the first and second electronic apparatuses; and a control unit adapted to connect the detection target mechanism to the first electronic apparatus where a connection between the first electronic apparatus and the second electronic apparatus is detected by the connection detecting unit. The present technology is applicable to, for example, a scenario in which a universal serial bus (USB) host recognizes connection to a USB device.

Abstract: In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. Each of the enable outputs of the switch is connected to an enable input of one of the non-volatile storage units. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Abstract: An automated device discovery system includes a chassis defining device slots, with device connectors located adjacent each of the device slots. A bus subsystem and a reset subsystem are coupled to the device connectors. A processing system, which is coupled to each of the at least one bus system and the reset subsystem, causes the reset subsystem to sequentially assert reset instructions through each of the device connectors in a device slot sequence. The processing system then sequentially detects, via bus paths in the bus subsystem, each device that is located in one the device slots and coupled to its respective device connector based on reset operations performed by that device in response to the sequentially asserted reset instructions. The processing system then maps each device that was detected with a respective device slot identifier that corresponds to the device slot sequence in which the reset instructions were asserted.

Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may control a write operation of a memory device in response to a write command received from a host. The memory controller includes a host interface, a buffer, and a first processor. The host interface is configured to receive write data corresponding to the write command from the host. The buffer is configured to store the write data. The first processor is configured to control operations of the host interface and the buffer. The first processor is configured to, when the write command is received, set an operation mode based on an operating status of the memory controller.

Abstract: Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.

Abstract: A hybrid docking station determines whether native video data exists and can be passed through to a video port or whether a virtual video processor should be activated to provide virtual video data to a video port. For example, a laptop is connected to a hybrid docking station using a USB™ 3.0 connection. The hybrid docking station recognizes that the USB™ 3.0 connection includes a native video data and passes the native video data to a DisplayPort™. By avoiding activating a virtualized video processor and using native video data, the laptop avoids installing software to communicate with the virtualized video processor and communicates with one or more displays using a native video channel. By avoiding installing software, it simplifies IT's and user's usage and experience with universal docking station.

Abstract: A system is described that performs memory access operations. The system includes a processor in a first node, a memory in a second node, a communication interconnect coupled to the processor and the memory, and an interconnect controller in the first node coupled between the processor and the communication interconnect. Upon executing a multi-line memory access instruction, the processor prepares a memory access operation for accessing, in the memory, a block of data including at least some of each of at least two lines of data. The processor then causes the interconnect controller to use a single remote direct memory access memory transfer to perform the memory access operation for the block of data via the communication interconnect.

Abstract: In a computer comprising a plurality of integrated circuits (ICs), each IC may be connected to all other ICs via a respective point-to-point interconnect. A source IC divides the data to be transmitted to a destination IC for a transaction to generate multiple data cells so that each data cell includes a different portion of the data. The source IC transmits one of the data cells to the destination IC and remaining data cells to intermediate ICs, wherein an intermediate IC is an IC other than the source IC or the destination IC. The intermediate ICs forward the remaining data cells to the destination IC.

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.