Patents Examined by Christopher Culbert
  • Patent number: 10483319
    Abstract: A pixelated display device and a method for making the same are disclosed. The device may include an array of nanowire LEDs located above a substrate. When the nanowire LEDs are initially grown, they may emit first-wavelength light proximally to the substrate and second-wavelength light distally from the substrate. The nanowires may remain as initially grown, in which case only second-wavelength light is visible, or the second-wavelength light emitting portions may be etched away such that only first-wavelength light is visible.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 19, 2019
    Assignee: GLO AB
    Inventors: Nathan Gardner, Ronald Kaneshiro, Daniel Bryce Thompson, Fariba Danesh, Martin Schubert
  • Patent number: 10439131
    Abstract: A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm ?m2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Manzar Siddik, Witold Kula, Suresh Ramarajan
  • Patent number: 10438836
    Abstract: A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer. The first insulating film is etched back to expose an upper portion of the fin-shaped semiconductor layer and a second resist is formed so as to be perpendicular to the fin-shaped semiconductor layer. The fin-shaped semiconductor layer is etched to form a pillar-shaped semiconductor layer, such that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles defines the pillar-shaped semiconductor layer.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 8, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10388841
    Abstract: A light emitting device may include a substrate; a body which is disposed on the substrate and has a first hole having a predetermined size and a light emitting chip which is disposed within a cavity formed by the substrate and the first hole of the body. A cap may be disposed on the body and may have a second hole having a predetermined size. A transparent window may be disposed in the second hole. A lower portion of the cap is divided into a first surface and a second surface more projecting downwardly than the first surface, and at least a portion of the first surface is attached and fixed to the body.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 20, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Byung Mok Kim, Hiroshi Kodaira, Su Jung Jung, Bo Hee Kang, Young Jin No, Yuichiro Tanda, Satoshi Ozeki
  • Patent number: 10290597
    Abstract: A semiconductor device according to an embodiment comprises a substrate, an epitaxial layer on the substrate, and a cluster including a plurality of particles disposed on the epitaxial layer, the particles being disposed to be apart from each other, and contacting the epitaxial layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 14, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Yeong Deuk Jo
  • Patent number: 10236315
    Abstract: Provided is a solid-state image pickup element including: a sensor unit configured to generate an electrical signal in response to incident light; a color filter covering the sensor unit; and a lens configured to concentrate the incident light into the sensor unit via the color filter and formed by a laminated film made of a predetermined lens material. The lens is formed on the color filter without providing a planarization layer for removing a difference in level in the color filter.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 19, 2019
    Assignee: Sony Corporation
    Inventors: Yutaka Ooka, Shinji Miyazawa, Kensaku Maeda, Atsushi Yamamoto
  • Patent number: 10193065
    Abstract: An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Chin-Wei Liang, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 10177275
    Abstract: An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 8, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10147727
    Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
  • Patent number: 10134863
    Abstract: Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu
  • Patent number: 10134786
    Abstract: Disclosed is an array substrate, a method of manufacturing the same, and a display device. The method of manufacturing an array substrate includes: forming a pattern comprising an active layer, a source, a drain, a data line and a pixel electrode on a base substrate through a single patterning process; forming a pattern of an insulating layer; forming a pattern comprising a gate and a gate line through a single patterning process. In the array substrate, the method of manufacturing the same, and the display device of the present invention, only two patterning processes are required to achieve the fabrication of the array substrate, which has less and simple process steps, thereby reduces the manufacturing complexity and manufacturing cost, and increasing the production efficiency and the economic benefit.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: November 20, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seongyeol Yoo, Seungjin Choi, Heecheol Kim, Youngsuk Song
  • Patent number: 10128370
    Abstract: A semiconductor device capable of increasing a value of current that flows through the whole chip until a p-n diode in a unit cell close to a termination operates and reducing a size of the chip and a cost of the chip resulting from the reduced size, and including a second well region formed on both sides, as seen in plan view, of the entirety of a plurality of first well regions, a second ohmic electrode located over the second well region, a third separation region of a first conductivity type that is positioned closer to the first well regions than the second ohmic electrode in the second well region and that is formed to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode located on the third separation region.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 13, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Shiro Hino, Koji Sadamatsu
  • Patent number: 10128405
    Abstract: A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 13, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stephan Kaiser, Andreas Ploessl
  • Patent number: 10128385
    Abstract: A semiconductor body of a first type of conductivity is formed including a base layer, a first further layer on the base layer and a second further layer on the first further layer. The base layer and the second further layer have an intrinsic doping or a doping concentration that is lower than the doping concentration of the first further layer. A doped region of an opposite second type of conductivity is arranged in the semiconductor body, penetrates the first further layer and extends into the base layer and into the second further layer. Anode and cathode terminals are electrically connected to the first further layer and the doped region, respectively. The doped region can be produced by filling a trench with doped polysilicon.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 13, 2018
    Assignee: ams AG
    Inventors: Jordi Teva, Frederic Roger
  • Patent number: 10096705
    Abstract: An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity semiconductor material in which a first well diffusion including a second polarity semiconductor material is formed. An outer wall of the first well diffusion is abutted to the substrate. A second well diffusion, having first polarity semiconductor material, is arranged inside the first well diffusion such that an outer wall of the second well diffusion abuts an inner wall of the first well diffusion. The structure includes a gate driver having high side positive and negative supply voltage ports, and a driver input and output. The gate driver includes a transistor driver in the second well diffusion such that control and output terminals of the transistor driver are coupled to the driver input and output, respectively.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Allan Nogueras Nielsen, Mikkel Høyerby
  • Patent number: 10079331
    Abstract: Various embodiments include semiconductor devices, such as nanowire LEDs, that include a plurality of first conductivity type semiconductor nanowire cores located over a support, a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, and a layer of a high index of refraction material over at least a portion of a surface of at least one of the nanowire cores and the shells, wherein the high index of refraction material has an index of refraction that is between about 1.4 and about 4.5. Light extraction efficiency may be improved.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 18, 2018
    Assignee: GLO AB
    Inventors: Scott Brad Herner, Xiaoming Ji
  • Patent number: 10068947
    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 10035696
    Abstract: Measures are provided, by which mechanical stresses within the diaphragm structure of a MEMS component may be intentionally dissipated, and which additionally enable the implementation of diaphragm elements having a large diaphragm area in comparison to the chip area. The diaphragm element is formed in the layer structure of the MEMS component. It spans an opening in the layer structure and is attached via a spring structure to the layer structure. The spring structure includes at least one first spring component, which is oriented essentially in parallel to the diaphragm element and is formed in a layer plane below the diaphragm element. Furthermore, the spring structure includes at least one second spring component, which is oriented essentially perpendicularly to the diaphragm element. The spring structure is designed in such a way that the area of the diaphragm element is greater than the area of the opening which it spans.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: July 31, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Fabian Purkl, Michael Stumber, Ricardo Ehrenpfordt, Rolf Scheben, Benedikt Stein, Christoph Schelling
  • Patent number: 10014347
    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 9960287
    Abstract: A passivation layer is deposited on a first portion of a region of the solar cell. A grid line is deposited on a second portion of the region. The passivation layer is annealed to drive chemical species from the passivation layer to deactivate an electrical activity of a dopant in the first portion of the region of the solar cell.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 1, 2018
    Assignee: PICASOLAR, INC.
    Inventors: Seth Daniel Shumate, Douglas Arthur Hutchings, Hafeezuddin Mohammed, Matthew Young, Scott Little