Patents Examined by Christopher Culbert
  • Patent number: 11393885
    Abstract: A display substrate includes a base substrate; and a single pixel definition layer on the base substrate defining a plurality of subpixel apertures. The single pixel definition layer includes a plurality of hydrophobic particles dispersed in a main body for enhancing hydrophobicity of a portion of the single pixel definition layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: July 19, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Wei Li, Jingjing Xia, Bin Zhou, Jun Liu, Yingbin Hu, Guangyao Li, Wei Song, Tongshang Su
  • Patent number: 11289477
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Blandine Duriez, Georgios Vellianitis
  • Patent number: 11251369
    Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 11239261
    Abstract: A display device having a gate driver which may reduce generation of ripple at the output of the gate drive includes: a substrate; and a driver circuit including a thin film transistor disposed on the substrate, the thin film transistor including: a first gate electrode disposed on the substrate; a semiconductor layer disposed on the first gate electrode to overlap a part of the first gate electrode, the semiconductor layer including channel, source, and drain regions; a second gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer and respectively connected to the source region and the drain region, wherein a first area formed by the overlapping portion of the first gate electrode and the drain region has a different size than a second area formed by the overlapping portion of the first gate electrode and the source region.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 1, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheol-Gon Lee, Il-Joo Kim, Mee Hye Jung, Jun Ki Jeong
  • Patent number: 11228018
    Abstract: An organic light-emitting display panel and a fabrication method thereof are provided. The organic light-emitting display panel comprises a substrate; an organic light-emitting device disposed on a side of the substrate, wherein the organic light-emitting device has a first side facing the substrate and an opposing side; and an encapsulation layer disposed on the opposing side of the organic light-emitting device. The encapsulation layer includes at least one organic encapsulation layer, and the at least organic encapsulating layer has a polymer network of cross-linked polyorganosiloxane.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: January 18, 2022
    Assignees: Shanghai Tianma AM-OLED Co., Ltd., Tianma Micro-Electronics Co., Ltd.
    Inventors: Jian Jin, Congyi Su
  • Patent number: 11222992
    Abstract: An optoelectronic component, comprising: a structured semiconductor layer, a metallic mirror layer arranged on the semiconductor layer, a diffusion barrier layer arranged on the metallic mirror layer, a passivation layer arranged on the diffusion barrier layer, wherein the semiconductor layer comprises a mesa structure with mesa trenches. The mesa trenches taper from the surface of the semiconductor layer towards the mirror layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 11, 2022
    Assignee: OSRAM OLED GmbH
    Inventors: Stephan Kaiser, Andreas Ploessl
  • Patent number: 11205709
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Patent number: 11195833
    Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 7, 2021
    Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
  • Patent number: 11183115
    Abstract: A method for forming a pixel circuit includes forming transistors on a substrate; forming a passivation layer over the transistors; forming a contact hole to a source of a transistor; forming a transparent conductor that forms a contact in the contact hole and a resistor to control pixel current; and forming an organic light emitting diode (OLED) with an anode connecting to the resistor.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 23, 2021
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 11158839
    Abstract: The present disclosure provides a composite film including a hydrophobic film layer and a hydrophilic film layer, a manufacture method thereof, and a light-emitting display device. The hydrophobic film layer is in contact with the hydrophilic film layer, and the hydrophilic film layer forms folds under an action of water vapor. As such, it is possible to achieve real-time detection of whether water vapor enters a light-emitting display device formed subsequently, and thus the adverse effects of water vapor on the light-emitting display device can be eliminated timely.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 26, 2021
    Inventor: Yanqiu Li
  • Patent number: 11139281
    Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
  • Patent number: 11127798
    Abstract: A pixel definition layer and a manufacturing method thereof, a display substrate, and a display panel are provided. The pixel definition layer includes: a lyophilic material layer on a base substrate, which includes a plurality of lyophilic portions spaced in pairs, which being with an annular structure and used to define a pixel region; and a lyophobic material layer on a side of the lyophilic material layer from the base substrate, which being filled between each two adjacent lyophilic portions of the plurality of lyophilic portions, and a distance from a surface of the lyophobic material layer from the base substrate to the base substrate is larger than a distance from a surface of the lyophilic material layer from the base substrate to the base substrate. The pixel definition layer improves the uniformity of films formed in the pixel region by the solution.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Linlin Wang, Chengyuan Luo
  • Patent number: 11088161
    Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 10, 2021
    Inventors: Taeyoung Kim, Moorym Choi, Dongchan Kim
  • Patent number: 11050034
    Abstract: A quantum dot (QD) light emitting diode comprising first and second electrodes facing each other; a QD emitting material layer between the first and second electrodes; and a semiconducting member acting as a hole transporting path in the QD emitting material layer is provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: June 29, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Tae-Yang Lee, Kyu-Nam Kim, Sung-Il Woo
  • Patent number: 11037923
    Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Stephen M. Cea, Barbara A. Chappell
  • Patent number: 11011566
    Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 18, 2021
    Inventors: Volume Chien, I-Chih Chen, Hsin-Chi Chen, Hung-Ta Huang, Ying-Hao Chen, Ying-Lang Wang
  • Patent number: 10992346
    Abstract: An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 27, 2021
    Assignee: NXP USA, Inc.
    Inventors: Fred T. Brauchler, Qiang Li
  • Patent number: 10981777
    Abstract: A MEMS transducer system includes a MEMS transducer device for sensing at least one of pressure signal or acoustic signal. The MEMS transducer device includes first and second diaphragms. Formed between the diaphragms are a spacer, plate capacitor elements, and electrode elements. The plate capacitor elements are coupled to the diaphragms via the spacer. An optional member may be disposed within the spacer. The distal ends of the electrode elements are coupled to a structure such as insulator element. An optional oxides may be formed within the plate capacitor elements. Pressure sensing electrode formed between the diaphragms may be coupled to the insulator element.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 20, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Andrew Doller, Gokhan Hatipoglu, Yujie Zhang, Bernhard Gehl, Daniel Christoph Meisel
  • Patent number: 10964687
    Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 30, 2021
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prahbu
  • Patent number: 10964796
    Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the base region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo