Abstract: Described herein are ruggedized wafer level MEMS force dies composed of a platform and a silicon sensor. The silicon sensor employs multiple flexible sensing elements containing Piezoresistive strain gages and wire bonds.

Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Abstract: In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region.

Abstract: The invention is directed to a method for forming a nitride on a silicon substrate. In the method of the present invention, a silicon substrate is provided and a buffer layer is formed on the silicon substrate. The formation of the buffer layer includes a multi-level temperature modulation process having a plurality temperature levels and a plurality of temperature modulations. For each of the temperature modulations, the temperature is gradually decreased. A nitride is formed on the buffer layer.

Abstract: Disclosed is a shallow trench isolation structure having an air gap for suppressing the dark currents and cross-talk which occur in CMOS image sensors. The shallow trench isolation structure suppresses photons injected from neighboring pixels and dark current, so that high-quality images are obtained. Since impurities are removed from a p type ion implantation region for a photodiode when an inner wall oxide layer is etched to form the air gap, the p type ion implantation region has a uniform doping profile, thereby suppressing the diffusion of electrons towards the surface and achieving an image having a high quality.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask.

Abstract: A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.

Abstract: Method for producing an MST device, and MST device A method for producing an electromechanical transducer is described, wherein an MST component is arranged in a container, and the container is closed with a cover layer, wherein the cover layer is provided with at least one cutout which divides the cover layer into an inner region and an outer region in such a way that both the inner region and the outer region are connected to the top side—facing the cover layer—of the MST component, and the inner region is lifted off while the outer region remains adhered.

Abstract: A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.

Abstract: A solid state light emitting device comprising an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of the active region. The active region emits light at a predetermined wavelength in response to an electrical bias across the doped layers. An absorption layer of semiconductor material is included that is integral to said emitter structure and doped with at least one rare earth or transition element. The absorption layer absorbs at least some of the light emitted from the active region and re-emits at least one different wavelength of light. A substrate is included with the emitter structure and absorption layer disposed on the substrate.

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Abstract: A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.