Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

Abstract: An image sensor utilizes a pure boron layer and a second epitaxial layer having a p-type dopant concentration gradient to enhance sensing DUV, VUV or EUV radiation. Sensing (circuit) elements and associated metal interconnects are fabricated on an upper surface of a first epitaxial layer, then the second epitaxial layer is formed on a lower surface of the first epitaxial layer, and then a pure boron layer is formed on the second epitaxial layer. The p-type dopant concentration gradient is generated by systematically increasing a concentration of p-type dopant in the gas used during deposition/growth of the second epitaxial layer such that a lowest p-type dopant concentration of the second epitaxial layer occurs immediately adjacent to the interface with the first epitaxial layer, and such that a highest p-type dopant concentration of the second epitaxial layer occurs immediately adjacent to the interface with pure boron layer.

Abstract: The present disclosure provides a method for processing a conductive structure. The method includes the following steps of: forming on a first surface a groove concave from the first surface towards a second surface by means of dry etching; extending the groove from the second surface to form a via through a silicon base; and processing a conductive structure within the via. The method can be applied to a silicon base having a thickness larger than 300 ?m. It breaks the limit on thickness that can be processed in the related art and is capable of providing electrical connectivity on both sides of a silicon base. The method is simple and highly reliable, has high processing efficiency and is applicable to mechanized production.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: A semiconductor device includes a single lead frame, a semiconductor element, and a mold material. The semiconductor element is joined onto one main surface of the lead frame. The lead frame includes a die-attach portion, a signal terminal portion, and a ground terminal portion. The die-attach portion, the signal terminal portion, and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along one main surface. A groove portion is provided by partially removing the lead frame so as to allow the groove portion to pass therethrough, the groove portion being provided between the die-attach portion and the ground terminal portion adjacent to each other in the lead frame and between the signal terminal portion and the ground terminal portion adjacent to each other in the lead frame.

Abstract: The display device includes a substrate including first and second sub pixels, a first electrode patterned in each of the first and second sub pixels on the substrate, a first emission layer in each of the first and second sub pixels on the first electrode to emit first colored light, a second electrode in each of the first and second sub pixels on the first emission layer, a second emission layer on the second electrode to emit second colored light, and a third electrode on the second emission layer. The first electrode of the first sub pixel is relatively larger than the first electrode of the second sub pixel, the first electrode of the first sub pixel is electrically connected with the second electrode of the first sub pixel, and the first electrode of the second sub pixel is insulated from the second electrode of the second sub pixel.

Abstract: A manufacturing method of an image sensing device includes the following steps. A substrate is provided. At least one image sensing unit is disposed in the substrate. A passivation layer is formed on the substrate. An auxiliary layer is formed on the passivation layer. A material composition of the auxiliary layer is different from a material composition of the passivation layer. An annealing process is performed to the substrate and the passivation layer. The passivation layer is covered by the auxiliary layer during the annealing process. The auxiliary layer is removed after the annealing process. The ability to constrain and/or passivate free charge in and/or near the passivation layer may be enhanced by performing the annealing process with the auxiliary layer covering the passivation layer. The electrical performance of the image sensing device may be improved accordingly.

Abstract: A method is presented for constructing a dual metal interconnect structure. The method includes forming a trilayer stack over a dielectric layer, forming a plurality of vias extending through the trilayer stack and into the dielectric layer, depositing a first conductive material to fill the plurality of vias, etching the first conductive material to form first conductive regions, depositing a spacer, etching the spacer to form spacer portions adjacent the first conductive regions, and depositing a second conductive material.

Abstract: The disclosure illustrates systems and methods for removing at least some excess gate material of a FinFET transistor. A FinFET transistor with the excess gate material removed may include a gate with a T-shaped cross-section. The narrower portion of the cross-section may be processed using backside wafer processing. The width of the narrower portion may be defined by a spacer.

Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.

Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.

Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: [Object] To make it possible to improve viewing angle characteristics more. [Solution] Provided is a display device including: a plurality of light emitting sections formed on a substrate. The light emitting section has a configuration in which a luminescence layer is sandwiched by a first electrode functioning as a reflecting electrode and a second electrode in a stacking direction, a surface of the first electrode facing the luminescence layer is inclined from a plane perpendicular to the stacking direction in at least a partial region in a display surface, and an inclination direction of the first electrode has a distribution in the display surface.

Abstract: A semiconductor device manufacturing method is presented. The manufacturing method includes: providing a semiconductor structure, wherein the semiconductor structure comprises a semiconductor substrate, a first doped region in the semiconductor substrate, and a first gate structure on the first doped region; forming a source and a drain in the first doped region on two opposing sides of the first gate structure; and implanting dopants to the source and the drain by an ion implantation process, wherein the implantation direction and an upper surface of the first doped region form an acute angle, the dopants implanted to the source and the drain have the same conductivity type as that of the source and the drain. In this method, the dopants are implanted at an acute angle, they improve the drain current of a transistor, and thus improve the performance of a semiconductor device.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.