Abstract: A method of fabricating a semiconductor device is disclosed in the present invention. The method includes the steps of forming first and second wells in the substrate, the first and second wells having first and second type conductivities, respectively, forming first, second, and third isolation layers in the substrate, forming first and second gate oxide layers on the first and second wells, forming first and second buried contact regions in the substrate, and forming first and second impurity regions in the first and second buried contact regions, and forming first and second gates on the first well and third and fourth gates on the second well, the first and fourth gates directly contacting the first and second buried contact regions, respectively.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by forming a separate well region around the emitter terminal and the collector terminal, the area of distribution of ions within the emitter terminal and the collector terminal of a lateral bipolar junction transistor is also enlarged.

Abstract: In accordance with the above first embodiment of the present invention, after a base polysilicon film has been grown, a lump anneal is carried out because of an extremely small variation to the silicon dioxide film. Subsequently, a buffered fluorine acid is used which has a large selective etching ratio of the silicon oxide film to the polysilicon film to side-etch the silicon oxide film in the horizontal direction by a predetermined width before the base impurity BF2+ is implanted and then the emitter polysilicon film is formed. For those reasons, a variation in distance between the n+-substrate and a collector is small. The base width “WB” of the base region is not varied, whereby variations in high frequency performance of the bipolar transistor are suppressed.

Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850° C. As the substrate is heated to a temperature of 1050° C., N+ dopant gas is injected into the carrier gas to suppress auto doping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080° C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080° C.

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract: The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). A step separate from the annealing step for the source/drain regions is utilized for annealing the gate conductor.

Abstract: A method of forming an improved Schottky diode structure as part of an integrated circuit fabrication process that includes the introduction of a selectable concentration of dopant into the surface of an epitaxial layer so as to form a barrier-modifying surface dopant layer. The epitaxial layer forms the cathode of the Schottky diode and a metal-silicide layer on the surface of the epitaxial layer forms the diode junction. The surface dopant layer positioned between the cathode and the diode junction is designed to raise or lower the barrier height between those two regions either to reduce the threshold turn-on potential of the diode, or to reduce the reverse leakage current of the transistor. The particular dopant conductivity used to form the surface dopant layer is dependent upon the conductivity of the epitaxial layer and the type of metal used to form the metal-silicide junction.

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). A second disposable gate structure (28) of the second, complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A capping layer (60) may be formed over the first and second regions (16, 18) including the first and second disposable gate structures (26, 28). A portion (62, 64) of the first and second disposable gate structures (26, 28) may be exposed through the capping layer (60). A second disposable gate cap (66) may be formed over the exposed portion (64) of the second disposable gate structure (28) and at least part of the first disposable gate structure (26) removed.

Abstract: A manufacturing method of a bipolar transistor that can reduce, without increasing capacitance between base-collector, withstand voltage deterioration and leakage between emitter-base is provided. On an upper surface of an active area of a semiconductor substrate on which an isolation structure is formed by a first insulating film, a first epitaxial growth layer is formed. Then, on an upper surface of a first epitaxial growth layer a third insulating layer is formed in an area larger than that of the first epitaxial growth layer. Thereafter, from a side surface of a first epitaxial growth layer, a second epitaxial growth layer is formed in an area larger than that of a third insulating layer. Thereafter, all over the surface of the semiconductor substrate a first poly-silicon layer, a fourth and fifth insulating layers are formed, an opening is opened with an area approximately equal with that of an active area, and inside the opening a second poly-silicon layer and emitter layer are formed.

Abstract: A method for forming an adapted small dimension and more quality fabrication is disclosed. In one embodiment, the present invention provides a twin gate CMOS, which includes isolations formed in a semiconductor substrate. A P-well and an N-well inside the semiconductor substrate are formed and isolated by an isolating region. Next, a gate oxide layer and a first polysilicon layer are formed sequentially above the P-well and an N-well. A polysilicon layer doped in-situ with N-type ions. Sequentially, a first oxide layer is deposited and a first photoresist layer is formed on the polysilicon layer above P-well region, wherein etching respective patterns on the first oxide layer and the polysilicon layer. An amorphous silicon layer doped with P-type ions by implanation is formed over the gate oxide layer and the first oxide layer above the semiconductor substrate. After forming a second oxide layer on the amorphous silicon layer.

Abstract: A new method is provided for the conduction of heat between a flip-chip and the motherboard and heatsink onto which the flip-chip is mounted. In a flip-chip package of the invention the heatsink is in direct contact with the flex circuit, the contact balls of the flip chip make contact with the flex circuit. The flip-chip is attached and reflow is performed thereby attaching the contact balls to the flex circuit. The flip chip is encased in a molding compound in a one step process procedure that is in accordance with Ser. No. 09/640,534, assigned to a common assignee. The flip-chip is now placed on the motherboard with the contact balls and the underfill facing upwards. The underfill provides direct contact between the flip-chip and the flex circuit/heatsink. This direct contact significantly increases the heat flow between the flip-chip and the heatsink.

Abstract: An encapsulant molding technique used in chip-on-board encapsulation wherein an oxidizable metal layer is patterned on a substrate and the oxidizable metal layer is oxidized to facilitate removal of unwanted encapsulant material. The oxidizable metal layer which adheres to the substrate is applied over a specific portion of the substrate. The oxidizable metal layer is oxidized to form a metal oxide layer which does not adhere to encapsulant materials.

Abstract: A method of preparing small wafers for compatibility with conventional large wafer fabrication equipment comprising the following steps: indenting a face of a large wafer to form an array of depressions thereon, each depression sized to matingly accept a lower portion of a small wafer; applying a bonding medium to an exterior side of the depressions on the indented face of the large wafer; matingly fitting the small wafers into the depressions so that the small wafers are positioned in an array on the large wafer; and, removing the top portion of the small wafers standing out of the depressions by chemical mechanical polishing so that the remaining portions of the small wafers then have a uniform thickness generally equal to the depth of the indentations in the large wafer. A preferred aspect of this invention provides for a method as above wherein the small wafer is SiC and the large wafer is made from an amorphous substance which comprises SiC or aluminum nitride.

Abstract: An aspect of the present invention is a method for making a functional active device (photodetector, laser, LED, optical modulator, optical switch, field effect transistor, MOSFET, MODFET, high electron mobility transistor, heterojunction bipolar transistor, resonant tunneling device, Esaki tunneling device etc.) disposed over a complementary metal oxide semiconductor (CMOS) device, having the steps; (a) forming an ultrathin compliant layer direct bonded to an oxide layer over said-CMOS device; (b) growing an epitaxial layer on said ultra-thin compliant layer (c) forming a functional active device in said epitaxial layer grown on said epitaxial layer that is grown on said ultrathin compliant layer; and (c) interconnecting said functional active device and said CMOS device, wherein said CMOS device is configured as either a readout circuit or a control circuit for said photodetector.

Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: An array substrate of a liquid crystal display device has a glass substrate on which gate lines, signal lines, pixel electrodes, and thin-film transistors are arranged. Each of the thin-film transistors includes a gate electrode composed of a part of one of the gate lines and including a first conductive layer formed on the glass substrate and a second conductive layer covering the first conductive layer. A gate insulating film is formed on the glass substrate and covers the gate electrode. A thin non-single-crystal silicon film is disposed on the gate insulating film on the gate electrode and includes a channel region. Source and drain electrodes are connected electrically to the thin non-single-crystal silicon film.