Abstract: A dimmer conduction angle detection circuit, and systems and methods incorporating the same, is disclosed. The circuit receives a gate drive signal from a PFC circuit and provides a dimmer reference level signal representative of a dimmer circuit's dimmer setting in response. The circuit includes a comparator with first and second inputs that provides a pulse-width modulated output in response to comparing signals received at the inputs. The pulse-width modulated output has a pulse width representative of the dimmer circuit's dimmer setting. The circuit also includes an input network, coupled to the comparator, to receive the gate drive signal and to provide an output, in response, to the comparator's first input. The circuit also includes a threshold supply circuit to provide a threshold voltage to the comparator's second input, and a filter, coupled to the comparator, to convert the comparator's pulse-width modulated output to the dimmer reference level signal.

Abstract: A novel Integrated Circuit device including a plurality of antifuse-configurable interconnect circuits, each circuit including: at least two interconnects, and at least one antifuse, wherein the antifuse is adapted to directly connect at least two interconnects. The Integrated Circuit device also includes a plurality of transistors adapted to configure at least one antifuse of the antifuse-configurable interconnect circuits, wherein the transistors are above the antifuse-configurable interconnect circuits.

Abstract: The present invention provides in a first aspect a programmable interconnect network for an array of logic blocks, which comprises a plurality of switch boxes being connected in a tree-based hierarchical architecture and providing selection and connection for the logic blocks, switch boxes located at the lowest level of the tree structure are connected to the logic blocks; wherein said network comprises a crosslink established between two of said plurality of switch boxes. The present invention helps implement functions with more area and timing efficiency and/or placement-friendliness.

Abstract: According to one embodiment, a digital filter circuit includes an EXOR circuit, a clock gating circuit, a reset control circuit, a counter, a filter time setting circuit, a comparator, and a decoder. The clock gating circuit outputs a clock gating signal. The reset control circuit generates a first signal. The counter generates a count signal. The filter time setting circuit latches the count signal when the first signal is in the enable state, and outputs a latched count value as a second signal. The comparator receives the count signal and the second signal, and outputs a third signal of the enable state when the value of the count signal and the value of the second signal match each other.

Abstract: An automatic vehicle identification (AVI) system signal processing technique which provides improved performance and reliability and which substantially eliminates the adverse effect of ambient noise signals on the detection of permissible code sequences by an AVI receiver. Input signals to an AVI receiver are filtered to strip off all frequency components except those at the carrier frequency. The filtered signals are subjected to variable gain amplification over a substantially linear operating range with the maximum amplitude of the amplified signals limited to a maximum value below the supply voltage and within the linear range of the variable gain amplifier. The amplified signals are converted to a binary pulse train signifying the temporal length of each active carrier period and the temporal length of each quiescent carrier period. The binary pulse train is decoded and a valid vehicle signal is generated if the decoded binary pulse train matches a permissible code sequence.

Abstract: A method of facilitating push-to-talk (PTT) communications between a server device and a client device using SIP-based messaging, the server device being in communication with a media server. The method includes receiving in the server device from the client device a SUBSCRIBE message for subscription to a push-to-talk group, the SUBSCRIBE message including media information of the client device, storing in the server device the media information of the client device, and sending from the server device to the client device a NOTIFY message, the NOTIFY message including media information of the media server for storage by the client device.

Abstract: A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices.

Abstract: The invention relates to an electronic candle and an electronic night lamp. The electronic candle includes a light-emitting diode (LED), a capacitor and a control circuit. The capacitor has a first terminal coupled to a first terminal of the LED, and a second terminal coupled to a common voltage. The control circuit has a first control terminal coupled to the first terminal of the LED, and a second control terminal coupled to a second terminal of the LED. In a detecting period, the control circuit provides a preset voltage across the first and second terminals of the LED so that the LED is reversely biased for a preset time. Then, the first control terminal of the control circuit is set to high impedance. Next, the control circuit detects a variation of a voltage of the first terminal of the capacitor with respect to time to determine whether to light up the LED.

Abstract: A communication network for a fleet of vehicles is disclosed. The communication network has a first group of the fleet of vehicles having a first level of priority on the network and a second group of the fleet of vehicles having a second level of priority on the network. A first vehicle in the first group is assigned as a supervisor of a second vehicle in the second group.

Abstract: Ballasts are presented with improved end-of-life (EOL) detection of lamp DC voltage components and protection circuits to facilitate user maintenance and extend lamp life using selective dimming with preheating when EOL conditions are detected.

Abstract: The present invention of a reverse polarity series type LED is formed by two sets of LED and diode assemblies in reverse polarity series connection wherein the first set is consisted of at least one or multiple homopolar series or parallel connected or series and parallel connected LED's, and the second set consisting of at least one or more homopolar parallel or series connected or series and parallel connected LED's for further connection to the drive circuit formed by current-limiting impedance and/or power storage and discharging devices and/or voltage-limit circuit devices in order to produce the required operational characteristics.

Abstract: A personal digital assistant includes a body, and a touch panel. The body includes a display screen. The touch panel is located on a surface of the display screen. The touch panel includes at least one transparent conductive layer including a carbon nanotube layer.

Abstract: Techniques are described that can be used to determine a transmitter power level of a mobile station at cell edge. To determine transmitter power level, the technique considers at least a balance of power transmitted by mobile stations near cell edge and power transmitted by mobile stations closer to cell center, target mean received power by the base station from mobile stations near center cell, target mean power transmitted from cell edge mobile stations, signal-to-interference-power ratio between signals transmitted from base stations of different cells to the mobile station at cell edge, and channel gain.

Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A capacitive full-wave circuit for LED light strings makes use of capacitors and diodes together to drive a LED string with full AC waves. Different from the conventional four-diode full-wave rectifying circuit, one embodiment of capacitive full-wave circuit includes two capacitors and two diodes. Because of the large imaginary impedance, the capacitors not only limit and the voltage and current through the LEDs, but also consume almost no electrical power. The electrical current-voltage performance can be further improved by introducing four resistors with a cost of some additional power consumption. A LED light string module with the capacitive full-wave circuit is also presented, with the capacitive full-wave circuit integrated inside of a front power plug and a back power socket.

Abstract: An analog-to-digital converter (ADC) implements non-uniform conversion accuracy so as to allow for high conversion accuracy for a select narrower input range while also accommodating a wider overall input range and requiring fewer conversion bits compared to conventional ADCs. The ADC includes an ADC core that receives an input signal and outputs a first digital value having a first number of bits, the first digital value based on the input signal and an accuracy configuration of the ADC core. The ADC also includes an encoder to generate a second digital value have a second number of bits, greater than the first number of bits, based on the first digital value and the accuracy configuration of the ADC core. The ADC further includes an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold.

Abstract: A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.

Abstract: Embodiments of the present invention provide for the rapid reignition of a high intensity discharge lamp. In one embodiment of the invention, an apparatus for a fast reigntion of a high intensity discharge lamp is disclosed. The apparatus is comprised of a ballast operatively coupled to the lamp that is configured to receive power from a power supply. The apparatus is also comprised of a timer circuit that enters a timing phase and produces a quantum of timing information when the lamp ceases receiving power from the power supply. This timer circuit does not require external power during the timing phase. The apparatus is additionally comprised of a control circuit that receives the timing information and permits the ballast to reignite the lamp based on the information.

Abstract: An LED driver controller comprises a voltage regulator for controlling an output voltage to a top of a plurality of LED strings responsive to at least a reference voltage. A plurality of first circuitries each associated with a node at a bottom of each of the plurality of LED strings compares a voltage at the bottom of each of the plurality of LED strings with a high reference voltage and a low reference voltage. Control logic generates a first control signal when the voltage at the bottom of each node of the plurality of LED strings exceeds the high reference voltage and generates a second control signal when the voltage at least one of node of the plurality of LED strings falls below the low reference voltage. Second circuitry responsive to the first control signal and the second control signal generates the reference voltage.